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Altera_Forum
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13 years ago

FPGA Newbie Q's - Cyclone IV

Apologies if this is the wrong forum. Am new to FPGA development and have a Q I've not been able to resolve in my readings. Would appreciate help...

The FPGA comes with X LUTs and Y memory bits (I understand the difference here). I need to create a "memory array" within a component that is 10kx1. Do I create this as a register (i.e., reg MyArray[0..10000])? Or is there another way to define a memory array? The component will be accessed with an address and will provide read/write access to the array.

Thanks, in advance, for your help....

ME

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    You can do it that way, since it's one bit. Open your Verilog file in Quartus and go to Edit -> Insert Template -> Verilog -> Full Designs and there should be some inferred memory examples.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thank you both for your help.....

    One more newbie Q..

    The component I am building has a single bit output that gets connected to two other component inputs. I am using SOPC builder and defined the output as an export. However, I don't see it show up in the SOPC builder GUI that allows me to connect it to the other components.

    Am quite sure that I don't have a complete grasp on SOPC builder paradigm yet. Any advice is appreciated...

    ME
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    If you exported it you are going to see it on the instantiation template and you need to connect them in your top design or wherever you are going to instantiate it.

    If you want it to be an internet signal in the SOPC you can't export it.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    What is the signal that you are trying to connect? There might be a good chance of it falling under a standard interface type which you would declare in component editor and then wire it up to other standard interfaces in your system (masters, slaves, clocks, resets, streaming source/sink). Often when I have asynchronous wire or bus to connect between two custom cores I just jam them into an Avalon streaming source/sink pairing so that the tools will connect them together for me.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thanks BadOmen (and all). Your advice got me to point B. If you don't mind, you'll see another 1 or two threads pop up from me. Any help is appreciated.