Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

FPGA Newbie Q's - Cyclone IV

Apologies if this is the wrong forum. Am new to FPGA development and have a Q I've not been able to resolve in my readings. Would appreciate help... The FPGA comes with X LUTs and Y memory b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

What is the signal that you are trying to connect? There might be a good chance of it falling under a standard interface type which you would declare in component editor and then wire it up to other standard interfaces in your system (masters, slaves, clocks, resets, streaming source/sink). Often when I have asynchronous wire or bus to connect between two custom cores I just jam them into an Avalon streaming source/sink pairing so that the tools will connect them together for me.