FPGA n00b PCB design

I understand, that you referred to figure 10-7 in-system programming of serial configuration devices. It has nothing to do with JTAG but is using the dedicated AS programming interface. JTAG programming of AS is shown in figure 10–29 programming serial configuration devices in-system using the jtag interface. But both variants are possible. The latter requires an additional step (programming file conversion) but can utilize an existing JTAG interface, e. g. used for debug or boundary scan.

I also understand that you use a circuit according to figure 10–6 multi-device as configuration in which devices receive the same data with a single sram object file. From Altera publications, it's clear that AS devices must use 3.3V VCCIO for bank 1. This setting is also checked by Quartus software.

I'm not aware of any Altera specification regarding the necessary AS buffers, on the other hand many warnings have been issued not to use buffers in (single device) AS configuration. I would probably use a fast buffer with low input capacitance, e. g. 74AUP1G34. The suitable number of buffers depends on PCB topology, there should be no longer stubs. Also the Altera comments regarding source series termination should be considered.

Regarding the intended 2-layer design. I think, that's not completely impossible but very difficult, when I see the large percentage of connected IO pins. Apart from possible EMC and signal quality issues, I wonder if the additional effort in PCB routing will finally pay? Also the PCB probably could be somewhat smaller with better routing on a multilayer board. That's a large cake sheet anyway.

Another important point is SSO (simultaneous switching outputs) noise. This would be a big issue with 128 outputs as such, but worse with 2-layer PCB and large QFP240 case. It could be meaningful to take some precautionary measures as driving the clock differentially to the chip. However, I see a danger of possible design failure due to SSO noise.

--- Quote Start ---

I understand, that you referred to figure 10-7 in-system programming of serial configuration devices. It has nothing to do with JTAG but is using the dedicated AS programming interface. JTAG programming of AS is shown in figure 10–29 programming serial configuration devices in-system using the jtag interface. But both variants are possible. The latter requires an additional step (programming file conversion) but can utilize an existing JTAG interface, e. g. used for debug or boundary scan.

--- Quote End ---

That's correct, Fig. 10-7. JTAG was a misnomer on my part - it's just the configuration that I'm concerned with.

--- Quote Start ---

I also understand that you use a circuit according to figure 10–6 multi-device as configuration in which devices receive the same data with a single sram object file. From Altera publications, it's clear that AS devices must use 3.3V VCCIO for bank 1. This setting is also checked by Quartus software.

--- Quote End ---

Correct. And great to hear a solid confirm of the 3.3V requirement.

--- Quote Start ---

I'm not aware of any Altera specification regarding the necessary AS buffers, on the other hand many warnings have been issued not to use buffers in (single device) AS configuration. I would probably use a fast buffer with low input capacitance, e. g. 74AUP1G34. The suitable number of buffers depends on PCB topology, there should be no longer stubs. Also the Altera comments regarding source series termination should be considered.

--- Quote End ---

Looks like a great choice - thanks!

--- Quote Start ---

Regarding the intended 2-layer design. I think, that's not completely impossible but very difficult, when I see the large percentage of connected IO pins. Apart from possible EMC and signal quality issues, I wonder if the additional effort in PCB routing will finally pay? Also the PCB probably could be somewhat smaller with better routing on a multilayer board. That's a large cake sheet anyway.

--- Quote End ---

First of all, one thing that I should have mentioned in my first post is that size is no object, as the PCB is required to be an 18" diameter circle because of physical constraints of the application. I've uploaded a png of a portion of my current layout to http://jamesnsears.com/temp/sears_altera_001.png As you can see, I've bussed the three voltages around the inside of the ring of pins to leave the I/O pins accessible, and the bottom layer free for ground fill (not yet depicted). In three of the corners of the FPGA are 1.2, 2.5, and 3.3V regulators. I can certainly get the board routed this way, and am pretty close to having things figured out, but that is only useful of course if it will work when it's finished!

--- Quote Start ---

Another important point is SSO (simultaneous switching outputs) noise. This would be a big issue with 128 outputs as such, but worse with 2-layer PCB and large QFP240 case. It could be meaningful to take some precautionary measures as driving the clock differentially to the chip. However, I see a danger of possible design failure due to SSO noise.

--- Quote End ---

OK, so now I'm a little scared. Does the following help me though? Each of the 128 switching I/Os is driving a low gate charge (max .4nC, typ .29nC) MOSFET though a relatively short PCB trace that, as I calculate it from the microstrip formula, should have a capacitance of around 3pF max (narrow trace on a thicker than usual PCB), so this light load should help, right? Is there anything I can do with 2 layers to help increase the chance of success? What could I do on a 4-layer board to make things better? Do I even have a prayer here?

Thanks very much for your time.

-JNS

Regarding AS programming: Figure 10-7 is O.K. so far, however I have switched to SFL AS programming through JTAG. This is cause I always have JTAG interface in my designs and can avoid an additional connector and protection circuit. But as you have only one AS device, the additional part count and space requirement can be probably neglected, if JTAG is used at all.

Also with small load capacitance (and minimum drive strength) SSO may be an issue, I think. The effect can be seen even with a large number of unloaded pins switching simultaneously, only due to internal pin capacitance. It will cause VCCIO voltage drops and (more problematic) ground bounce, that is coupled e. g. to clock inputs, resulting possibly in PLL loss of lock. PQFP240 package has as a disadvantage long connection lengths with higher inductance, compared e. g. to FBGA. With 2-layer PCB, some additional inductance in ground and supply connections could be expected.

I have experienced SSO issues only with Cyclone II PQFP package devices up to now, the few Cyclone III designs probably have been less critical due to other design parameters, I yet can't say for sure, that the situation has improved with Cyclone III. However, this could be expected regarding PLL problems, cause an internal PLL analog supply regulator has been introduced with Cyclone III.

If you have an option to achieve time-displaced switching with your outputs, I would try to utilize it as a precaution.

--- Quote Start ---

Regarding AS programming: Figure 10-7 is O.K. so far, however I have switched to SFL AS programming through JTAG. This is cause I always have JTAG interface in my designs and can avoid an additional connector and protection circuit. But as you have only one AS device, the additional part count and space requirement can be probably neglected, if JTAG is used at all.

--- Quote End ---

Great, I think I'll just stick with 10-7 since I don't need JTAG for this app.

--- Quote Start ---

Also with small load capacitance (and minimum drive strength) SSO may be an issue, I think. The effect can be seen even with a large number of unloaded pins switching simultaneously, only due to internal pin capacitance. It will cause VCCIO voltage drops and (more problematic) ground bounce, that is coupled e. g. to clock inputs, resulting possibly in PLL loss of lock. PQFP240 package has as a disadvantage long connection lengths with higher inductance, compared e. g. to FBGA. With 2-layer PCB, some additional inductance in ground and supply connections could be expected.

I have experienced SSO issues only with Cyclone II PQFP package devices up to now, the few Cyclone III designs probably have been less critical due to other design parameters, I yet can't say for sure, that the situation has improved with Cyclone III. However, this could be expected regarding PLL problems, cause an internal PLL analog supply regulator has been introduced with Cyclone III.

--- Quote End ---

This is somewhat encouraging, as at least on the dev board my HDL design worked fine driving 128 unconnected pins. Of course there are a number of things working against me in the case of my hardware, like the package, 2 layer PCB, etc. Still good to know.

--- Quote Start ---

If you have an option to achieve time-displaced switching with your outputs, I would try to utilize it as a precaution.

--- Quote End ---

By this do you just mean staggering the switching in my design, or some other chip-specific feature?

In your mind, am I correct to say that it seems that it's worth trying this on a 2 layer board, keeping these issues in mind? Also, do you have any pointers on where I might find resources on implementing a differential clock as you suggested in the earlier post?

Any thoughts on the power layout as seen here: http://jamesnsears.com/temp/sears_altera_001.png

Thanks again,

-JNS.

Yes, I meant just staggering the switching time. Of yourse with PWM, the duty cycle is arbitrary, but an equipartition of start time would paraobaly reduce simultaneous swiching.

I have used 2-layer PCB for prototypes and some simple FPGA production designs. Basically I would rely more on maximum usage of bypass capacitors and an almost continuous ground plane at the bottom than on thick supply traces, but the shown supply wiring is acceptable, I think. I'm not sure, how the design will look including signal wiring, but I would give it a try.

Regarding differential clock supply, I was aware that Cyclone III doesn't support a differential IO standard with 3.3V VCCIO. With Cyclone II, e. g. LVPECL could be used. So I think, the option isn't usable in your design.

On the SSO issue. One thing you can do to reduce this problem, is tone down the output drivers. By default Quartus puts very strong output drivers, but you can make them 2 mA drivers, which will go along way. Still worth insuring minimal simultaneous switching, but it helps a-lot.

I didn't look at your layout, but it would be interesting to know how it works in the end.

--- Quote Start ---

On the SSO issue. One thing you can do to reduce this problem, is tone down the output drivers. By default Quartus puts very strong output drivers, but you can make them 2 mA drivers, which will go along way. Still worth insuring minimal simultaneous switching, but it helps a-lot.

--- Quote End ---

Thanks for the input, I'll definitely take advantage of the lower output drivers. I'm currently debating whether to run the bulk of the I/O at 2.5 or 3.3V (the SD card needs 3.3V and I'm attracted to the simplicity of having them all be the same).

--- Quote Start ---

I didn't look at your layout, but it would be interesting to know how it works in the end.

--- Quote End ---

I'll definitely keep you all posted. If all goes well (and maybe even if it doesn't!) the Discovery Channel will be shooting the end of the process next month for a show called Daily Planet, so you may get a chance to see things come together on screen.

I appreciate everyone's input. I'm still working on this so I of course welcome any more ideas!

Thanks,

-JNS.