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I understand, that you referred to figure 10-7
in-system programming of serial configuration devices. It has nothing to do with JTAG but is using the dedicated AS programming interface. JTAG programming of AS is shown in figure 10–29
programming serial configuration devices in-system using the jtag interface. But both variants are possible. The latter requires an additional step (programming file conversion) but can utilize an existing JTAG interface, e. g. used for debug or boundary scan.
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That's correct, Fig. 10-7. JTAG was a misnomer on my part - it's just the configuration that I'm concerned with.
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I also understand that you use a circuit according to figure 10–6
multi-device as configuration in which devices receive the same data with a single sram object file. From Altera publications, it's clear that AS devices must use 3.3V VCCIO for bank 1. This setting is also checked by Quartus software.
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Correct. And great to hear a solid confirm of the 3.3V requirement.
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I'm not aware of any Altera specification regarding the necessary AS buffers, on the other hand many warnings have been issued not to use buffers in (single device) AS configuration. I would probably use a fast buffer with low input capacitance, e. g. 74AUP1G34. The suitable number of buffers depends on PCB topology, there should be no longer stubs. Also the Altera comments regarding source series termination should be considered.
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Looks like a great choice - thanks!
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Regarding the intended 2-layer design. I think, that's not completely impossible but very difficult, when I see the large percentage of connected IO pins. Apart from possible EMC and signal quality issues, I wonder if the additional effort in PCB routing will finally pay? Also the PCB probably could be somewhat smaller with better routing on a multilayer board. That's a large
cake sheet anyway.
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First of all, one thing that I should have mentioned in my first post is that size is no object, as the PCB is required to be an 18" diameter circle because of physical constraints of the application. I've uploaded a png of a portion of my current layout to
http://jamesnsears.com/temp/sears_altera_001.png As you can see, I've bussed the three voltages around the inside of the ring of pins to leave the I/O pins accessible, and the bottom layer free for ground fill (not yet depicted). In three of the corners of the FPGA are 1.2, 2.5, and 3.3V regulators. I can certainly get the board routed this way, and am pretty close to having things figured out, but that is only useful of course if it will work when it's finished!
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Another important point is SSO (simultaneous switching outputs) noise. This would be a big issue with 128 outputs as such, but worse with 2-layer PCB
and large QFP240 case. It could be meaningful to take some precautionary measures as driving the clock differentially to the chip. However, I see a danger of possible design failure due to SSO noise.
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OK, so now I'm a little scared. Does the following help me though? Each of the 128 switching I/Os is driving a low gate charge (max .4nC, typ .29nC) MOSFET though a relatively short PCB trace that, as I calculate it from the microstrip formula, should have a capacitance of around 3pF max (narrow trace on a thicker than usual PCB), so this light load should help, right? Is there anything I can do with 2 layers to help increase the chance of success? What could I do on a 4-layer board to make things better? Do I even have a prayer here?
Thanks very much for your time.
-JNS
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