FPGA n00b PCB design

Regarding AS programming: Figure 10-7 is O.K. so far, however I have switched to SFL AS programming through JTAG. This is cause I always have JTAG interface in my designs and can avoid an additional connector and protection circuit. But as you have only one AS device, the additional part count and space requirement can be probably neglected, if JTAG is used at all.

Also with small load capacitance (and minimum drive strength) SSO may be an issue, I think. The effect can be seen even with a large number of unloaded pins switching simultaneously, only due to internal pin capacitance. It will cause VCCIO voltage drops and (more problematic) ground bounce, that is coupled e. g. to clock inputs, resulting possibly in PLL loss of lock. PQFP240 package has as a disadvantage long connection lengths with higher inductance, compared e. g. to FBGA. With 2-layer PCB, some additional inductance in ground and supply connections could be expected.

I have experienced SSO issues only with Cyclone II PQFP package devices up to now, the few Cyclone III designs probably have been less critical due to other design parameters, I yet can't say for sure, that the situation has improved with Cyclone III. However, this could be expected regarding PLL problems, cause an internal PLL analog supply regulator has been introduced with Cyclone III.

If you have an option to achieve time-displaced switching with your outputs, I would try to utilize it as a precaution.