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Amir21's avatar
Amir21
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4 years ago

FPGA MAX10 in "User-Mode" indication

Hi,

I'm using DPRs in MAX10-FPGA and init their memory through .hex files.

In order to verify when the FPGA initialization process done,

I'm trying to use the "INIT_DONE" output pin for inidication to release the FPGA external reset signal.

Apparently, I can't find it and enable this pin (INIT_DONE) in Quartus 20.1.1 in the output options.

I'll be glad to know what other possibilities I can use in order to get inidcation for the FPGA enters into "User-Mode" ?

Thanks!

11 Replies

  • sstrell's avatar
    sstrell
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    4 years ago

    I think you're looking for CONF_DONE, not INIT_DONE, which you have enabled there.

    • Amir21's avatar
      Amir21
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      4 years ago
      Hi,
      Since in my design I'm using DPRs which initialized from HEX files, I need to know when the initialization process done.

      I'm looking for any valid indication from the FPGA to indicate when it entered into 'USER-MODE' (initialization process finished).
    • Amir21's avatar
      Amir21
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      4 years ago
      Hi,
      That's exactly the issue..
      The 'CONF_DONE' indication is not enough, I need to know when the initialization process has done..

      I tried to find out from the spec how can I use the MAX10 'INIT_DONE' through the Quartus tool, with no success..
  • NurAiman_M_Intel's avatar
    NurAiman_M_Intel
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi,


    Since INIT_DONE is not mention in the User guide, then there is not INIT_DONE can be check.


    The other option is, you can check the status of the I/O pin as per your design. In user mode, the user I/O pins will then function as specified by your design.


    Regards,

    Aiman


    • Amir21's avatar
      Amir21
      Icon for New Contributor rankNew Contributor
      4 years ago
      Hi,
      Sounds like a good idea, I will definitely try it.

      In addition,
      Any idea until when the FPGA reset should remain valid, when we use the DPR IP in my design?

      Best Regards,
      Aizik Amos.
    • Amir21's avatar
      Amir21
      Icon for New Contributor rankNew Contributor
      4 years ago
      Hi,
      I actually meant to the IP Component -
      RAM: 2-Port

      Best Regards,
      Aizik Amos.
  • NurAiman_M_Intel's avatar
    NurAiman_M_Intel
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you