Altera_Forum
Honored Contributor
Honored ContributorFPGA Master Driven Coherent Memory Transactions Using Write/Read Masters on Linux
Hi,
I'm trying to compare 3 fpga master driven memory transaction scenarios on altera cyclone v soc: - Connecting to SDRAM controller directly, - Connecting to SDRAM controller using F2H bridge, - Connecting to scu through acp using F2H bridge. .. and - I'm running linux - I use msgdma write/read IP's as FPGA Masters. I allocate contiguous memory using cma kernel feature combined with texas instrument cmem api. Naturally MSGDMA is controlled via Linux driver. I would appreciate help with the usage of ACP port.current progress. Following the documentation (9-29 in Cyclone V Device Handbook): SCU is enabled (checked manually), SMP bit in ACTLR is set (checked manually), I have no access to page map configuration, but I assume allocated coherent memory is marked shareable due to the fact, that I use both ARM cores, I target ACP in physical memory region (0x80000000 base address), After reset ID Mapper is in dynamic state, Write/Read Masters use Avalon interfaces not AXI, so they don't drive AxUSER and AxCACHE signals!!! These signals are generated by memory interconnect. here i get dizzy... In documentation it is stated, that ACP ID mapper can control overriding signals for AXI masters that cannot drive the sideband signals themselves. BUT... it is stated that this is not true for FPGA Masters. so i conclude that i must drive these signals myself. I went into source code and set these AxUSER and AxCACHE signals manually!! I tried setting AxCACHE[1] and AxUSER[0] to 1. there were noticeable changes in transfer speed (2x-3x), but transactions still weren't coherent. Then I set AxUSERS signal to "11111" and AxCACHE to "1111". Again there were changes in transaction speeds. I find this quite a challanging task and finally here is my question:Is it possible to use ACP with an FPGA master through memory-mapped interconnect. And if that's so, what am I missing here?
