FPGA Master Driven Coherent Memory Transactions Using Write/Read Masters on Linux

success!!! i'm overwhelmed! :)

Problem was hiding in the Texas Instruments CMEM API driver I've been using!

So..., CMA Kernel feature allows dma_alloc_coherent() to dynamically allocate large buffers of contiguous memory. CMEM API while mapping physical address to user space sets page protection settings (As I see it, some of these settings are architecture dependent). I can't find good documentation about these parameters for ARM, so if you know good source - please post it!

I found flags in "arch/arm/include/asm/pgtable-2level.h":

# define l_pte_mt_uncached (http://lxr.free-electrons.com/ident?i=l_pte_mt_uncached) (_at (http://lxr.free-electrons.com/ident?i=_at)(pteval_t (http://lxr.free-electrons.com/ident?i=pteval_t), 0x00) << 2) /* 0000 */

#define l_pte_mt_bufferable (http://lxr.free-electrons.com/ident?i=l_pte_mt_bufferable) (_at (http://lxr.free-electrons.com/ident?i=_at)(pteval_t (http://lxr.free-electrons.com/ident?i=pteval_t), 0x01) << 2) /* 0001 */

#define l_pte_mt_writethrough (http://lxr.free-electrons.com/ident?i=l_pte_mt_writethrough) (_at (http://lxr.free-electrons.com/ident?i=_at)(pteval_t (http://lxr.free-electrons.com/ident?i=pteval_t), 0x02) << 2) /* 0010 */

#define l_pte_mt_writeback (http://lxr.free-electrons.com/ident?i=l_pte_mt_writeback) (_at (http://lxr.free-electrons.com/ident?i=_at)(pteval_t (http://lxr.free-electrons.com/ident?i=pteval_t), 0x03) << 2) /* 0011 */

#define l_pte_mt_minicache (http://lxr.free-electrons.com/ident?i=l_pte_mt_minicache) (_at (http://lxr.free-electrons.com/ident?i=_at)(pteval_t (http://lxr.free-electrons.com/ident?i=pteval_t), 0x06) << 2) /* 0110 (sa1100, xscale) */

#define l_pte_mt_writealloc (http://lxr.free-electrons.com/ident?i=l_pte_mt_writealloc) (_at (http://lxr.free-electrons.com/ident?i=_at)(pteval_t (http://lxr.free-electrons.com/ident?i=pteval_t), 0x07) << 2) /* 0111 */

#define l_pte_mt_dev_shared (http://lxr.free-electrons.com/ident?i=l_pte_mt_dev_shared) (_at (http://lxr.free-electrons.com/ident?i=_at)(pteval_t (http://lxr.free-electrons.com/ident?i=pteval_t), 0x04) << 2) /* 0100 */

#define l_pte_mt_dev_nonshared (http://lxr.free-electrons.com/ident?i=l_pte_mt_dev_nonshared) (_at (http://lxr.free-electrons.com/ident?i=_at)(pteval_t (http://lxr.free-electrons.com/ident?i=pteval_t), 0x0c) << 2) /* 1100 */

#define l_pte_mt_dev_wc (http://lxr.free-electrons.com/ident?i=l_pte_mt_dev_wc) (_at (http://lxr.free-electrons.com/ident?i=_at)(pteval_t (http://lxr.free-electrons.com/ident?i=pteval_t), 0x09) << 2) /* 1001 */

#define l_pte_mt_dev_cached (http://lxr.free-electrons.com/ident?i=l_pte_mt_dev_cached) (_at (http://lxr.free-electrons.com/ident?i=_at)(pteval_t (http://lxr.free-electrons.com/ident?i=pteval_t), 0x0b) << 2) /* 1011 */

#define l_pte_mt_vectors (http://lxr.free-electrons.com/ident?i=l_pte_mt_vectors) (_at (http://lxr.free-electrons.com/ident?i=_at)(pteval_t (http://lxr.free-electrons.com/ident?i=pteval_t), 0x0f) << 2) /* 1111 */

#define l_pte_mt_mask (http://lxr.free-electrons.com/ident?i=l_pte_mt_mask) (_at (http://lxr.free-electrons.com/ident?i=_at)(pteval_t (http://lxr.free-electrons.com/ident?i=pteval_t), 0x0f) << 2)

Yeah..., my assumption that memory is marked shared seems to be incorrect. It might be shared between processor cores, but it is not shared with other peripherals (devices). Anyway, I used l_pte_mt_dev_shared flag and data seems to be cached (dummy data creation done by HPS is 5x faster when compared with uncached memory), and transferred data passes validation.

in conclusion.

acp port can be used with avalon-mm masters, but AxCACHE and AxUSERS signals must be set directly (by default Qsys interconnect pulls them to the ground).

I'm planning to summarize all this into a tutorial (in couple of months). Give me notice if interested! ;)