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Honored ContributorFPGA Master Driven Coherent Memory Transactions Using Write/Read Masters on Linux
Hi, I'm trying to compare 3 fpga master driven memory transaction scenarios on altera cyclone v soc: - Connecting to SDRAM controller directly, - Connecting to SDRAM controller using F2H br...
Altera_ForumHonored Contributor
Honored ContributorRihards,
So I've been having trouble consistently using FPGA to HPS bridge (and SDRAM memory hooked directly to the CPU) with larger buffers (not sure about the smaller ones) so I'd like to ask for your help. I'm using Linux too and have a custom vhdl IP that I set up to write data to memory (4M buffer). My device driver simply uses "dma_alloc_coherent" to allocate the buffer and the ioctl's control the IP one of which is to enable writing to the 4M buffer. What I see on signal tap is that the IP starts to write to the memory BUT after 15 writes the "avm_waitrequest" is asserted so nothing else happens. The IP is waiting for the HPS side to do it's thing... Do you happen to have any insight into this? Any suggestions? Thanks in advance.
