Honored Contributor
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I actually ended up writing driver to allocate contiguous cached/noncached memory to userspace :rolleyes:. The code is available here: http://git.edi.lv/rihards.novickis/fpsoc_linux_drivers (http://git.edi.lv/rihards.novickis/fpsoc_linux_drivers). The driver is called cma, there are still some features I should implement... Anyway check the USAGE file and please give me some feedback :) page protection. Regarding page protection flags - for cached memory I used the default ones provided by the mmap() syscall. See the cma/driver/cma.c file, cma_mmap(...) function. sideband signals. I'm not sure whether this is the problem You are having, but actually my problem was on the hardware side. Internally ARM uses AXI interface, but the MSGDMA cores work with Avalon interface, thus Qsys actually generates special interconnect to connect these interfaces. For ACP to work, You need to assert special side-band signals present in AXI, but not present in Avalon. Default values for these side-band signals are set through Qsys interconnect, so if You want Your DMA core to be able to access cached memory You have to manually set them after Qsys system generation. Haha, this is quite dirty and you have to redo this after every Qsys generation. I passed the default value of these signals in generated top entity file, I use VHDL, so for me it is hps_system.vhd. In the code it looks something like this (and I'm not 100% about the requirement of reasserting prot signals): f2h_AWCACHE => "1111", -- .awcache f2h_AWPROT => "000", -- .awprot f2h_AWUSER => "11111", -- .awuser f2h_ARCACHE => "1111", -- .arcache f2h_ARPROT => "000", -- .arprot f2h_ARUSER => "11111", -- .aruser Anyway, I suggest using RTL viewer to check whether these signals are asserted correctly. As a proof of this working :D, here is graph of measured speeds where You can observe that transaction speed reduces when "packet" size is comparable with L2 cache :) https://www.alteraforum.com/forum/attachment.php?attachmentid=14235 I hope this helps!
