Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

FPGA Master Driven Coherent Memory Transactions Using Write/Read Masters on Linux

Hi, I'm trying to compare 3 fpga master driven memory transaction scenarios on altera cyclone v soc: - Connecting to SDRAM controller directly, - Connecting to SDRAM controller using F2H br...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hey!

Some directions I would follow:

- Is FPGA-HPS bridge enabled? (under "/sys/class/fpga_bridge")

- Then I would check whether the data is actually written to the memory (while using non cached memory, at first).

- If data is not there => How do You pass physical address to Your DMA IP core?

I would be glad to look into it myself, of course if Your core is not under NDA or something...