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Altera_Forum
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9 years ago

FPGA Master Driven Coherent Memory Transactions Using Write/Read Masters on Linux

Hi, I'm trying to compare 3 fpga master driven memory transaction scenarios on altera cyclone v soc: - Connecting to SDRAM controller directly, - Connecting to SDRAM controller using F2H br...
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Altera_Forum
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8 years ago

I was incorrect, l_pte_mt_dev_shared stands for something else and this memory is not cached, although initialization was even faster then for memory acquired with malloc (I suppose explanation could be lazy allocation, still curios though, why it was faster then simply noncached memory).

Nevertheless, additionally PROT signal had to be set to ground.

So in conclusion:

- cache, user signals set high,

- prot signal set low,

- Access only through dedicated ACP window ( address | 0x80000000 ).

Note: this will work only with cached memory via acp. connection to sdram via f2h bridge and noncached memory will not work.