Howdy, With the Cyclone IV FPGA, we have run into some issues with noise on Vccio and Vccint pins while using the 24 mA default drive current. I found an application note (http://www.altera.com/support/kdb/solutions/rd04062007_606.html?gsa_pos=1&wt.oss_r=1&wt.oss=power%20drive%20current) that mentions that the drive current affects the device power draw (obviously), but I can't find any quantification of this effect. Can anyone help me? I don't need an exact equation (although that would be nice) - even just a rough idea of the magnitude of the effect would be helpful. Thanks, Kathryn Turner

The linked application doesn't say anything about effects of drive strength on VCCIO current consumption. It's mainly talking about short circuit currents, which isn't your problem I guess. Basically. adjustment of IO strength is done by activating one or more output transistors. Because the IO node capacitance isn't changed, the dynamic power consumption can be expected unaffected by this adjustment. You affect however the output peak current and as result VCCIO noise and ground bounce. In contrast, I wouldn't expect changes to VCCINT dynamic currents. Regarding peak VCCIO and GND currents, why not simply assuming a proportional relation to IO drive strength. It can't be very wrong.

Reduce the drive current on the pins to help reduce noise on VCCIO. Although you shouldn't be getting significant noise on VCCIO with proper bypass. Also consider phasing the I/O outputs if you are driving a lot of them at once to help reduce noise and ground bounce. Jake

Thanks. That information helps. If you are curious, lowering the drive current to 8 mA does solve the problem (Reed-Solomon decoder fails, to be exact), but our customer thinks that reducing the drive current is a "band-aid" rather than a solution. Our application historically has zero errors even over very long periods of continuous operation, so naturally, we and the customer expect similar performance from our new version. They're concerned that there is an underlying problem that might show up after deployment. So the reason I asked is that I'm looking for information to convince the customer (and myself) that reducing the drive current really is a solution.

Facing errors with higher drive strength is actually a kind of alarm sign. If you have a large number of synchronous switching outputs, some ground bounce can't be avoided. But you should check, if the ground wiring and supply bypassing is sufficient in your PCB.

Are you sure it's VCCIO noise that's causing your product to fail? What are the main differences between this product and the previous version? Is it running significantly faster? Using different voltages? Handling more channels? The PCB must be different right? Just because a 24mA drive strength setting worked in one setting doesn't mean it will work in another. A 24mA drive strength on the I/O is too strong for many applications (most I dare say) and may result in significant ringing on the signals. Perhaps this is your problem rather than VCCIO noise. You should select a drive strength that gives the cleanest signal for your PCB design and termination scheme while still giving you adequate speed. Pounding all of your I/O with dramatic voltage swings and high dynamic current loads really isn't best practice. It may very well be that your new board is designed better than the previous one and you have lower parasitics on the signals making a 24mA drive strength too strong. Or it may also be that your PCB design is the problem. If it's really VCCIO and VCCINT noise that's the problem (I'd be surprised), this can be reduced by putting more effort into the design of your power delivery network. Basically you get noise on the rail because the power delivery network is unable to respond quickly enough to the dynamic current demands. It's impossible to remove all noise. Your choice of regulator, inductance, decoupling capacitor sizes, quantity, and types, PCB plane capacitance, via inductance all play a role in the regulator's ability to respond to those demands. Jake

FPGA drive current effect on power draw in Cyclone IV

13 Replies

Altera_Forum
Honored Contributor
16 years ago
Thanks. That information helps.

If you are curious, lowering the drive current to 8 mA does solve the problem (Reed-Solomon decoder fails, to be exact), but our customer thinks that reducing the drive current is a "band-aid" rather than a solution. Our application historically has zero errors even over very long periods of continuous operation, so naturally, we and the customer expect similar performance from our new version. They're concerned that there is an underlying problem that might show up after deployment. So the reason I asked is that I'm looking for information to convince the customer (and myself) that reducing the drive current really is a solution.
Altera_Forum
Honored Contributor
16 years ago
Reduce the drive current on the pins to help reduce noise on VCCIO. Although you shouldn't be getting significant noise on VCCIO with proper bypass. Also consider phasing the I/O outputs if you are driving a lot of them at once to help reduce noise and ground bounce.

Jake
Altera_Forum
Honored Contributor
16 years ago
The linked application doesn't say anything about effects of drive strength on VCCIO current consumption. It's mainly talking about short circuit currents, which isn't your problem I guess. Basically. adjustment of IO strength is done by activating one or more output transistors. Because the IO node capacitance isn't changed, the dynamic power consumption can be expected unaffected by this adjustment. You affect however the output peak current and as result VCCIO noise and ground bounce. In contrast, I wouldn't expect changes to VCCINT dynamic currents.

Regarding peak VCCIO and GND currents, why not simply assuming a proportional relation to IO drive strength. It can't be very wrong.

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FPGA drive current effect on power draw in Cyclone IV

13 Replies

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