FPGA drive current effect on power draw in Cyclone IV

Thanks. That information helps.

If you are curious, lowering the drive current to 8 mA does solve the problem (Reed-Solomon decoder fails, to be exact), but our customer thinks that reducing the drive current is a "band-aid" rather than a solution. Our application historically has zero errors even over very long periods of continuous operation, so naturally, we and the customer expect similar performance from our new version. They're concerned that there is an underlying problem that might show up after deployment. So the reason I asked is that I'm looking for information to convince the customer (and myself) that reducing the drive current really is a solution.