FPGA drive current effect on power draw in Cyclone IV

The linked application doesn't say anything about effects of drive strength on VCCIO current consumption. It's mainly talking about short circuit currents, which isn't your problem I guess. Basically. adjustment of IO strength is done by activating one or more output transistors. Because the IO node capacitance isn't changed, the dynamic power consumption can be expected unaffected by this adjustment. You affect however the output peak current and as result VCCIO noise and ground bounce. In contrast, I wouldn't expect changes to VCCINT dynamic currents.