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Altera_Forum
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13 years ago

FPGA cyclone EP1C12Q240C8n

Hello everyone,

I am trying to develop a FPGA(EP1C12Q240C8n) based vibration measuring system.The signal processing circuit of the vibration sensor gives 4 analog voltage signal as output. Next these signals are fed to FPGA kit where I have to perform the following task:

1. 12 bit ADC conversion for 4 analog signals and storing the digital output in RAM.

2. Designing a digital processing circuit to perform various arithmetic operations (i.e. summing ,multiplying ,square rooting etc) with the stored datas in RAM .

3. After that I would like to analyze the stored data from RAM to show the maximum, minimum value, frequency, positive and negative discrete values of amplitude with continuous changing input.

so plz tell me how i can store the timing data as well as changing amplitude in a RAM, and from this RAM how can i access the datas

plz guide me.

th

thank you

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    First it all depends on the ADC you are using and how it is interfaced to the FPGA. When you talk about RAM, is it memory inside the FPGA or an external RAM chip?

    If it is an internal memory you can declare your RAM as an array in HDL and access it directly. If it is an external component you will either have to write your controller, or use avalon interfaces and SOPC builder / QSys.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    i am using AD7864 (ADC) which is a 12 bit bipolar ADC. i am using .bdf design file to interface this ADC with FPGA kit, through byte-blaster download cable. now i want to store the digital data, after ADC conversion in a specific RAM ( which is a internal ram available in board ).Next i want to display and analysis the stored data from that RAM which are real time datas.

    Please kindly help me

    Thank You
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    When you say "internal ram available in board", you still mean a memory external to the FPGA, right? In that case I suggest using SOPC Builder or QSys, and write your component with an Avalon Memory Mapped Master to read/write the RAM, and an exported interface for the ADC.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    acctully my problem is that, i like to access real time data which is store in ram in FPGA kit. for that purpose i am using signal tap ii analyzer. am i wrong? or is there any other way to analyze real time signal

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Signaltap can analyse any register inside the FPGA so you can indeed use it to capture your ADC data as it gets in, or the results of some operations, or the data you read from or write to the memory.

    If you are using FPGA internal memory in a single port configuration, you can access its contents in real time using the In-System Memory Content Editor. If you are using it in a double port configuration, or using external memory, you will need to provide a means of access, for example using a JTAG-to-Avalon component and System Console.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thank you very much Daixiwen for your reply.

    actually i am using right now signal tap ii, its gives me hex values of ADC output. now if i like to reconstruct the original signal, or if i want to see the amplitude vs time graph from that hex values of signal tap ii, than it is possible or not .

    Is there any way to see that type of graph, because i like to find out the maximum amplitude as well as the minimum amplitude with time.

    so please if it is possible than help me.

    Thank you
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I have never used it, but I think you can select a "bar" or "line" format in Bus Display Formats in signaltap to display a vector as a graph.

    You can also implement your own logic to detect minimum and maximum values, it isn't very difficult to do.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thank youn again Daixiwen

    Plz tell me. whether i have to create that logic?

    through coding, or is therer any option in signaltapii to give that logic forcefully?

    Plz help me

    Thank you
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Through coding, preferably in VHDL or Verilog. You can integrate it in the part that receives the ADC data.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    i am using .bdf for design ADC as well as ram. actully i dont know it is right way or wrong, to connect ADC with RAM using .bdf.

    Because when i try to connect Ram with ADC i am getting no output from RAM when i see in signal tap ii window. may be write address signal(wraddr) , which is an input to Ram is not working properly. i can't understand this signal (wraddr)is connected to the which output pin of ADC.

    so please tell me it is possible to connect ADC with RAM using .bdf is possible or not...

    Thank you