Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

FPGA cyclone EP1C12Q240C8n

Hello everyone, I am trying to develop a FPGA(EP1C12Q240C8n) based vibration measuring system.The signal processing circuit of the vibration sensor gives 4 analog voltage signal as output. Nex...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

i am using .bdf for design ADC as well as ram. actully i dont know it is right way or wrong, to connect ADC with RAM using .bdf.

Because when i try to connect Ram with ADC i am getting no output from RAM when i see in signal tap ii window. may be write address signal(wraddr) , which is an input to Ram is not working properly. i can't understand this signal (wraddr)is connected to the which output pin of ADC.

so please tell me it is possible to connect ADC with RAM using .bdf is possible or not...

Thank you