FPGA configuration time and PCIe secification

Almost all PC systems cycle the PSU (except 5v standby) during reboot.

Windows 'restart' always does a full system reboot.

--- Quote Start ---

this HP laptop ( Windows 7 ) says Start -> Restart will "close all programs , shutdown Windwos and restart windows .... That really isn't sufficient unless the Windows driver enumerates the PCI again.

--- Quote End ---

Have you tried it? I'm working with a COUGH Virtex7 COUGH board at the minute and get exactly that message. The power isn't cut so the FPGA image is

maintained but the PCIe reset line must be driven active as the system enumerates the board OK.

This is what I'd expect to happen in any system.

--- Quote Start ---

Almost all PC systems cycle the PSU (except 5v standby) during reboot.

Windows 'restart' always does a full system reboot.

--- Quote End ---

I have never seen this behaviour, a restart has always kept the FPGA board configuration.

This is on at least 6 different systems I've developed PCI and PCIe boards on over the years!

Nial.

Thanks Nial,

I have tried the start -> move mouse to the shutdown box -> select restart.

I got to thinking to try start -> then enter restart in the search rectangle and a restart executable was found and when I ran it .... it did exactly what I wanted.

( of interest is that the same executable is not found in this HP Windows 7 laptop, but is on the HP 220 deskside I purchased for to get PCIe Gen3 slots ??? for PCIe work )

The Windows shut down, screen blanked, and POST / BIOS restarted without the power being cycled off and on. I use PCIscope to display the PCI system status.

That tool seems good for Windows, is there a Linux equivalent one ?

and the example Altera DMA application ran.

Didn't seem to fix the issue but I was able to get the FPGA Development card to come up , be recognized when run in slot 1 ... the x4 / x8 Gen2 slot .

The development card is configured for X8 Gen2 and I made sure the X1, X4, X8 present# signals were switched to just X8. Switches may have been in the wrong position ?

I have a feeling that possibly the slots in this system may be set to support certain speeds and a certain set of lane widths .

I can test this by trying to reconfigure the card for X1 Gen2 and change the capability switch for X1 present# and see if it still trains and

is identified in the same slot.

Thanks for all the help.... I can now go ahead and add the NIOS II and our own IP to the Stratix -V development board.

Any ideas on simpler boards supporting PCIe X1, X4, X8 @ Gen3, Gen2, Gen1 speeds with a Stratix -V and some external DDR memorty.

Best Regards , Have a great Friday,

Bob Dixon.

--- Quote Start ---

I plan to use Active Serial Configuration scheme to configure EP4CGX22 from EPCS4 on a custom PCIe x 4 board.

--- Quote End ---

You cannot meet the configuration timing using AS mode. The handbook states that AS mode cannot support PCIe. You're on the right track for determining what timing parameters are needed, but if you use the worst-case values for the AS mode parameters, then you cannot hit the 100ms window.

You need to use a MAX II CPLD plus flash (eg., QSPI Flash) and Fast Passive Serial or Parallel configuration mode.

Cheers,

Dave

--- Quote Start ---

You're on the right track for determining what timing parameters are needed, but if you use the worst-case values for the AS mode parameters, then you cannot hit the 100ms window.

Cheers,

Dave

--- Quote End ---

What are the worst-case values for the AS mode parameters for EP4CGX22 + EPCS4 bundle?

I mean - everything besides configuration time to transfer bitstream.

Knowing it I can calculate how many bits of configuration file will go through the rest of 100 ms window and only after this I can see - will my project squeeze in.

--- Quote Start ---

You cannot meet the configuration timing using AS mode. The handbook states that AS mode cannot support PCIe.

Cheers,

Dave

--- Quote End ---

Here is a card that will change Your mind: http://devboards.de/en/home/boards/product-details/article/db4cgx15/

For PCIe x 1 it uses EP4CGX15BF14C6N + EPCS16 in AS mode.

Will or will not AS mode support PCIe depends on how big and how well compressed is Your *.pof ( *.jic ) file , that is transferred in AS mode.

In my case the compressed *.pof ( *.jic ) file size is about 3.500.000 bits , that makes the reconfiguration time itself about 3.500.000 bits/40Mhz= 87.5 ms.

But what are the rest of worst-case values: POR-related, etc. ?

Will they squeeze into 100 - 87.5 = 12.5 ms ?

Can You please help to determine them?

It seems to me, that You once calculated them for EP4CGX15 in one of Your papers.

--- Quote Start ---

What are the worst-case values for the AS mode parameters for EP4CGX22 + EPCS4 bundle?

I mean - everything besides configuration time to transfer bitstream.

Knowing it I can calculate how many bits of configuration file will go through the rest of 100 ms window and only after this I can see - will my project squeeze in.

--- Quote End ---

Starting with the Cyclone IV Handbook (CYIV-5V1-1.9)

http://www.altera.com/literature/lit-cyclone-iv.jsp

p172 of the PDF, Table 8–3, has the MSEL options for the GX devices - you would select AS Fast POR mode.

p450, Table 1–3, indicates that the power supply ramp time must be tRAMP < 3ms for fast POR mode.

p176, Table 8–6, has the "AS DCLK Output Frequency", showing the worst-case is 20MHz.

p473, Table 1–29, shows that the typical AS frequency is 33MHz.

p169, Table 8-2, has the configuration file sizes. The EP4CGX22 has a configuration bit-length of 7,600,040

At a DCLK of 20MHz, the configuration bit-stream time is 7,600,040/20MHz = 380ms.

So there's no need to add in the POR and configuration control signal delays, as the 100ms time is completely blown out by the worst-case configuration time.

Contrast this to using PS mode or FPP mode;

p200, Table 8–12, fDCLK(max) = 66MHz or 133MHz depending on the device.

If you want the bit-stream to configure in say 80ms, then fDCLK for PS mode must be 7,600,040/80ms = 95MHz. This is possible if you are using a device that can operate at up to 133MHz.

A more conservative solution is to use FPP mode.

p208, Table 8–13, fDCLK(max) = 66MHz or 133MHz depending on the device, i.e., the same as PS mode, but this time you transfer 8-bits of data for every DCLK period, so ... fDCLK for FPP mode must be 7,600,040/(8 x 80ms) = 95MHz/8 = 12MHz.

A MAX II CPLD plus a QSPI flash can easily operate at 12MHz, this means with FPP mode, there is no problem meeting the power-on requirement.

But you have to add two devices - is that expensive? No.

EPCS4 $13

http://www.digikey.com/product-detail/en/epcs4si8/544-1243-5-nd/703950

MAX II CPLD EPM240M100C5N $6

http://www.digikey.com/product-detail/en/epm240m100c5n/544-1706-nd/1136022

Micron/Numonyx N25Q Quad-SPI Flash

http://www.micron.com/products/nor-flash/serial-nor-flash

a 16Mbit device should be good, eg., N25Q016A11ESC40F, but they're not in stock, so lets go for a 128Mbit part

$3.07

http://www.digikey.com/product-detail/en/n25q128a13ese40e/557-1562-nd/3874288

So you see, a MAX II plus QSPI flash is *cheaper* than an Altera EPCS4.

Cheers,

Dave

--- Quote Start ---

Here is a card that will change Your mind: http://devboards.de/en/home/boards/product-details/article/db4cgx15/

For PCIe x 1 it uses EP4CGX15BF14C6N + EPCS16 in AS mode.

--- Quote End ---

Just because a board exists does not mean it meets the PCIe specification for all possible designs! :)

--- Quote Start ---

Will or will not AS mode support PCIe depends on how big and how well compressed is Your *.pof ( *.jic ) file , that is transferred in AS mode.

In my case the compressed *.pof ( *.jic ) file size is about 3.500.000 bits , that makes the reconfiguration time itself about 3.500.000 bits/40Mhz= 87.5 ms.

--- Quote End ---

That is too optimistic, since the handbook and measurements show that DCLK is typically 33MHz, i.e., 3500000/33MHz = 106ms, so you've already failed to meet the power-on requirement.

--- Quote Start ---

But what are the rest of worst-case values: POR-related, etc. ?

Will they squeeze into 100 - 87.5 = 12.5 ms ?

Can You please help to determine them?

--- Quote End ---

Sure, read the other post.

--- Quote Start ---

It seems to me, that You once calculated them for EP4CGX15 in one of Your papers.

--- Quote End ---

Yep, and I gave up trying to use AS mode. FPP mode is faster, and is not more expensive (other than in needing PCB real-estate for the MAX II and QSPI Flash).

Cheers,

Dave

On the HP system I have and the Altera Stratix -V development card with SignalTrap configured for a Power-up Trigger, I don't seem to capture the slot PERST_N signal

rising edge. However the card still comes up active and is enumerated. I am able to trigger on the PERST_N signal rising edge when I perform a restart operation and the FPGA remains powered up and running.

There is a possibility that if the power on PERST_N is long enough, say 100 ms, then if the FPGA is configuring during the 100mS , there is an additional 100 ms

from the end of the fundamental reset , PERST_N, until the FPGA needs to be ready to receive configuration requests. ( per Add-in Card System Architecture Checklist )

I guess I could use SignalTap with a power-on trigger to display the LTSSM ... but think a 2 channel scope will tell me more.

Not sure how to include an image here ...

I could compute the configuration time for the Stratix-V and figure out the endpoint card power rail stable time that will then start the configuration load via the MAX chip.