FPGA configuration time and PCIe secification

On the HP system I have and the Altera Stratix -V development card with SignalTrap configured for a Power-up Trigger, I don't seem to capture the slot PERST_N signal

rising edge. However the card still comes up active and is enumerated. I am able to trigger on the PERST_N signal rising edge when I perform a restart operation and the FPGA remains powered up and running.

There is a possibility that if the power on PERST_N is long enough, say 100 ms, then if the FPGA is configuring during the 100mS , there is an additional 100 ms

from the end of the fundamental reset , PERST_N, until the FPGA needs to be ready to receive configuration requests. ( per Add-in Card System Architecture Checklist )

I guess I could use SignalTap with a power-on trigger to display the LTSSM ... but think a 2 channel scope will tell me more.

Not sure how to include an image here ...

I could compute the configuration time for the Stratix-V and figure out the endpoint card power rail stable time that will then start the configuration load via the MAX chip.