Honored ContributorHi All,
I am trying to connect 22x8 bit (4MByte) flash memory on DE2 board via flash cfi controller. If I connect it to the Avalon tri-state bridge I got the following error: "signal tri_state master and signal cfi_flash must have the same data with". What should I do to fix it? Please check the attachment. Thanks!
Honored ContributorHi, if your CFI_flash is correct (data width and address width), then double clic on the tristate bridge, you have to define here address width, data width and how they are shared.
Honored ContributorHi,
Thanks for the replay. I know that what you mentioned, but I have no any additional options to adjust the data width of bus: - option 1: Incoming signals --> registered / non-registered - option 2: Shared signals --> data / address / read_n / write_n selecting I have attached screen captures from SoPC Builder. Where can I adjust it?Honored ContributorSorry, I hdid not see before :
In SOPC, connect you cfi_flash to avalon slave ! EDIT : forget this post :oops: the connections seem correct.Honored ContributorHi,
I cannot connect the flash to the slave just to the master. I have did this based on "'Nios II Flash Programmer User Guide" tutorial. Please check the screen capture, this is from that literature where flash is being connected to the master. Thanks!Honored ContributorYes ! you were right.
You use SOPC. which version of quartus do you use ? version 10 and 11 are transitions from SOPC to QSYS I reopen an old project on Quartus II v9.0 wich is similar, change the Data with to 8, 16, 32 I get no error like you :-/ (just overlap error for 32 bit width data) It is strange that in your tristate bridge allow you do NOT share the "data" bus ; since data are always shared !?! Have you build your SOPC yourself, or have you modified an existant SOPC ? You are not alone : http://www.alteraforum.com/forum/showthread.php?t=43230&p=178794#post178794 (not resolved here) Tristate bridge in QSYS (new SOPC from Quartus) is more difficult, but possible. hard to help you, Good luck !Honored ContributorI am using 12.1 sp1. I have found this another same problem on the forum, and asked for the solution, but I have not got response so far. I have not modified the tri-state bridge I am using the basic IP core. My problem is that I have no option to change the bus width to be fitted to the flash signal.
The Altera University program supports another flash IP core especially for DE2 board, it works in SoC but does not work with flash programmer of eclipse. It starts to write the memory addresses, but a little bit later I get this error: "Error Code: 8 for command..." I have the same issue like this, but the solution does not work for me: http://www.alteraforum.com/forum/showthread.php?t=30752 I will start to learn Qsys instead of SoC, that is recommended to use. If I know well, Quartus 13.0 just contains only Qsys. Thanks.Honored ContributorHello guys!
I'm trying to execute the memory test template. I select the option to test flash. I have checked in the system.h file that the name of the flash is /dev/ext_flash. But when I type in the same name in the nios console, it shows an error saying : could not open "/dev/ext_flash" any idea how to eliminate this error? Thanks in advance.. any advice is welcome.
