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Altera_Forum
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Honored ContributorFitter Question
In the verilog file, I define a LUT like this:
cycloneii_lcell_comb \fpu_exceptions:u6|out~40_I ( .dataa(\fpu_exceptions:u6|out_2[40] ), .datab(rst), .datac(\fpu_exceptions:u6|out~32 ), .datad(in), .combout(\fpu_exceptions:u6|out~40 )); defparam \fpu_exceptions:u6|out~40_I .sum_lutc_input = "datac"; defparam \fpu_exceptions:u6|out~40_I .lut_mask = "0F22"; But after the Fitter(Place & Route), the architecure of that LUT is dispalyed in the picture. The signals which linked with dataa, datab, datac, datad respectively are changed. And the mask of this LUT is changed too. How can I do to avoid those changes. http://www.alteraforum.com/forum/attachment.php?attachmentid=10691&stc=110 Replies
Altera_ForumHi Tim,
I believe the Quartus will help you fit accordingly. The more important question was the Quartus Fitted result correct? Have you try signal tap the design to see if it is correct.- Altera_Forum
Hi Tim,
I'm just wondering if you received any fitter error message during compilation? - Altera_Forum
Hi Irish,
There have no error message during compilation. - Altera_Forum
Hi Ah_zhi02,
The Fitted result is correct, and the result of signaltap is correct too. But I want to fix the location of signals. Can you help me? - Altera_Forum--- Quote Start --- Hi Ah_zhi02, The Fitted result is correct, and the result of signaltap is correct too. But I want to fix the location of signals. Can you help me? --- Quote End --- Can I change the settings of Analysis and Synthesis to get what I wanted?
- Altera_Forum--- Quote Start --- Hi Tim, I believe the Quartus will help you fit accordingly. The more important question was the Quartus Fitted result correct? Have you try signal tap the design to see if it is correct. --- Quote End --- Hi Ah_zhi02, The Fitted result is correct, and the result of signaltap is correct too. But I want to fix the location of signals. Can you help me?
- Altera_Forum--- Quote Start --- Hi Tim, I'm just wondering if you received any fitter error message during compilation? --- Quote End --- Hi Irish, There have no error message during compilation. Can I change the settings of Analysis and Synthesis to get what I wanted?
- Altera_Forum
Hi Tim,
I believe Quartus II will help to perform optimization during the Analysis and synthesis to get the optimal implementation of your code into the hardware. As long as the hardware functionality or simulation behavior is correct, I think it should be ok. - Altera_Forum
I am not aware if there is any specific setting that could avoid the Quartus II from the changes, however, you can further look into Quartus II -> Analysis & Synthesis Settings -> More Settings to see if there is any specific option that you could play around to see if can avoid the change.
- Altera_Forum--- Quote Start --- Hi Irish,There have no error message during compilation. Can I change the settings of Analysis and Synthesis to get what I wanted? --- Quote End --- I think you need to use ECO to make some tiny modification on you logic after fitting.
