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Altera_Forum
Honored Contributor
Honored ContributorFitter Question
In the verilog file, I define a LUT like this: cycloneii_lcell_comb \fpu_exceptions:u6|out~40_I ( .dataa(\fpu_exceptions:u6|out_2[40] ), .datab(rst), .datac(\fpu_exceptions:u6|out~32 ), ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi Tim, I believe the Quartus will help you fit accordingly. The more important question was the Quartus Fitted result correct? Have you try signal tap the design to see if it is correct. --- Quote End --- Hi Ah_zhi02, The Fitted result is correct, and the result of signaltap is correct too. But I want to fix the location of signals. Can you help me?
