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Altera_Forum
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11 years ago

Fitter Question

In the verilog file, I define a LUT like this: cycloneii_lcell_comb \fpu_exceptions:u6|out~40_I ( .dataa(\fpu_exceptions:u6|out_2[40] ), .datab(rst), .datac(\fpu_exceptions:u6|out~32 ), ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Hi Ah_zhi02,

The Fitted result is correct, and the result of signaltap is correct too. But I want to fix the location of signals. Can you help me?

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Can I change the settings of Analysis and Synthesis to get what I wanted?