Forum Discussion
Altera_Forum
Honored Contributor
11 years agoFitter Question
In the verilog file, I define a LUT like this: cycloneii_lcell_comb \fpu_exceptions:u6|out~40_I ( .dataa(\fpu_exceptions:u6|out_2[40] ), .datab(rst), .datac(\fpu_exceptions:u6|out~32 ), ...
Altera_Forum
Honored Contributor
11 years agoI am not aware if there is any specific setting that could avoid the Quartus II from the changes, however, you can further look into Quartus II -> Analysis & Synthesis Settings -> More Settings to see if there is any specific option that you could play around to see if can avoid the change.