FIR interpolator

Question

Hello guys !!

I'm trying to understand the FIR compiler interpolator.

I have a complex signal clocked at X MHz. Now I want to have it interpolated by a 3x factor so that the output frequency will be Y=3X MHz. Then I have generated a FIR with the FIR compiler megawizard using the autogenerated coefficients and selecting the multicycle structure so that I have an input data processed every 3 clock period and a new output every clock period.

Finally I have conected the clock port with the 3X clock, the ast_sink_data with the input data, the ast_sink_valid and the ast_source_ready to vcc.

By the way on the SpecAnal I do not see the clear baseband spectrum at the desired frequency but a strange mixed one. AM I missing anything ??

Thank you !!

altera_forum · Answer

Hello

Your data is being generated at 1X clock right? If I understood correctly you are sending the same data 3X to the IP. This will not work as expected, to upsample 3X you need to send your data and then send two "zeroed" data. E.g:

Original input data at the 1X clock: 0xA, 0x8, 0x1, 0xF

Input data to the FIR IP at 3X clock: 0xA, 0x0, 0x0, 0x8, 0x0, 0x0, 0x1, 0x0, 0x0, 0xF, 0x0, 0x0

Let me know if this helps

Thiago

altera_forum · Answer

--- Quote Start ---

Hello

Your data is being generated at 1X clock right? If I understood correctly you are sending the same data 3X to the IP. This will not work as expected, to upsample 3X you need to send your data and then send two "zeroed" data. E.g:

Original input data at the 1X clock: 0xA, 0x8, 0x1, 0xF

Input data to the FIR IP at 3X clock: 0xA, 0x0, 0x0, 0x8, 0x0, 0x0, 0x1, 0x0, 0x0, 0xF, 0x0, 0x0

Let me know if this helps

Thiago

--- Quote End ---

FIR compiler set as interpolator does not need zero insertion and it takes care of that in deciding number of multipliers as it breaks filter into polyphases.

If however you input into a single rate filter and want it to interpolate then you need to insert zeros but this wastes multipliers.

altera_forum · Answer

Thanks for the clarification Kaz. The OP should keep the ast_sink_valid low for two clock cycles between each valid data then?

altera_forum · Answer

I have always some issue..

Say I have a baseband signal of band 2MHz clocked at 15MHz. I want to interpolate it by a 4 factor with a 2 stages interpolation.

So I have created two fir interpolators with the fir compiler megawizard.

I have set the first interpolator with a 2x factor and a multicycle implementation so that an input is processed every 4 clocks period and a new output is genereated every 2 clocks period.

I have set the second interpolator with a 2x factor and a multicycle implementation so that an input is processed every 2 clocks period and a new output is genereated every 1 clocks period.

I have set to 47 the number of the coefficients, set the sample rate of the first interpolator at 15*2MHz and 15*2*2 MHz for the second interpolator. Then I've used the autogenerate coefficients button to generate the fixed point coefficient.

Finally I have clocked both the interpolators with the 4x clock, used a counter to set the sink_valid of the first interpolator only for a 1/4 period of the 4x clock, connected the source_valid of the first interpolator with the sink_valid of the second interpolator and set to vcc all the source_ready.

By the way if use a NCO to generate a tone at +-6MHz and observing the interpolated output I cann see aliasing centered at +-30MHz..

So it seems that the first interpolator is working good but the second does not.. any suggestions ?

Thank you !

altera_forum · Answer

the sample rate of first filter is 15Msps, that of second is 30Msps (as referred to input) but why not use one filter set to interpolation of 4 and save yourself the trouble.

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FIR interpolator

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