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Honored Contributor
Honored ContributorFIR interpolator
Hello guys !! I'm trying to understand the FIR compiler interpolator. I have a complex signal clocked at X MHz. Now I want to have it interpolated by a 3x factor so that the output frequen...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hello Your data is being generated at 1X clock right? If I understood correctly you are sending the same data 3X to the IP. This will not work as expected, to upsample 3X you need to send your data and then send two "zeroed" data. E.g: Original input data at the 1X clock: 0xA, 0x8, 0x1, 0xF Input data to the FIR IP at 3X clock: 0xA, 0x0, 0x0, 0x8, 0x0, 0x0, 0x1, 0x0, 0x0, 0xF, 0x0, 0x0 Let me know if this helps Thiago --- Quote End --- FIR compiler set as interpolator does not need zero insertion and it takes care of that in deciding number of multipliers as it breaks filter into polyphases. If however you input into a single rate filter and want it to interpolate then you need to insert zeros but this wastes multipliers.
