Fast frequency generation/ modulation

An I/O rate of 0.1MHz to 50MHz is pretty slow for FPGAs. Any device will do.

I would recommend looking at the low-end devices. If you do not need much logic, then the MAX II devices are good (there are now MAX V devices too). There are also the low-end Cyclone series devices (Cyclone III, IV, or V).

Cheers,

Dave

Hi Dave

Thanks for the info.

10% of duty cycle at 50MHz would require a 2ns pulse, would a lower end device definatly support that?

Thanks

hmmm thats what I though, I may have to work to "friendly" increments of PWM at different freq.

What parameter should I be looking for in device specifications that will determine the maximum speed pulse output?

thanks folks

--- Quote Start ---

10% of duty cycle at 50MHz would require a 2ns pulse, would a lower end device definitely support that?

--- Quote End ---

The smallest duty cycle would be a single clock period. Eg. lets say you use a clock frequency of 100MHz, then 10ns is your minimum pulse width.

If you need a 2ns pulse width, then you could use an LVDS transceiver operating at 500Mbps. You would need to check the LVDS specifications for the device. The Stratix II devices can definitely generate 2ns pulses.

However, 2ns seems like a really short pulse for a PWM operation.

What are you trying to do?

Cheers,

Dave

This then begs the question what parameter do I look for to find the maximum clock an FPGA can use?

I took a cursory (ill admit it was VERY cursory) glance at a few spec sheets for FPGAs, and they seemed not to be to happy to actually say what speed this might be...

I mean what is "high perfomance" for an FPGA these days? 100MHz? 1GHz?

Dave thanks for your transceiver suggestion I will follow that up in the morning.

Im sorry, though I do appreciate your help, I actually cant go into much detail about what Im doing, but basically the signal is used to switch a FET.

thanks again

--- Quote Start ---

This then begs the question what parameter do I look for to find the maximum clock an FPGA can use?

--- Quote End ---

The best way is to use the synthesis tool on a couple of basic designs; I/O pad to IOE register, IOE register to fabric register, fabric-to-fabric register, and then run a timing analysis. Yeah, its a PITA, but there is really no other way to get meaningful values. You can read datasheets until your eyes go numb.

--- Quote Start ---

I mean what is "high perfomance" for an FPGA these days? 100MHz? 1GHz?

--- Quote End ---

I'd expect at least 100MHz from any MAX II device. I run them at 125MHz, and get them pretty full. I'd expect Cyclone devices at core frequencies up to 200MHz, and Stratix IV and higher at core frequencies of 300MHz, and perhaps higher. Much higher than that and you run into thermal issues. If you can keep the chip cool, then you can run things warmer. The high-speed transceivers in the Stratix GX/GT series can operate at 6.5Gps to 10Gbps (depending on part and settings) and the LVDS SERDES can operate up to about 1.25Gbps. You can always use those interfaces to generate short pulses, but you may need external logic to convert it to a voltage that is useful to you, or to something with decent current drive.

--- Quote Start ---

Basically the signal is used to switch a FET.

--- Quote End ---

Look at the gate drivers from TI. They have drivers with deadtime control, eg., UCC27223PWP. This allows you to just generate a logic level PWM, and let the gate driver care about turning the power mosfet on while turning the synchronous mosfet off. Even if you application is not identical to this, perhaps you can re-task a gate driver.

http://focus.ti.com/lit/ds/symlink/ucc27223.pdf

Here's some power supply design notes that may have some FET stuff of interest:

http://www.ovro.caltech.edu/~dwh/carma_board/power_supply_design_v1.59.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/power_supply_design_v1.59.pdf)

Cheers,

Dave

Stratix devices support DDR2, I haven't tried working with DDR 2 but i am assuming it probably could do 300 mhz DDR, or basically 600mhz.

And I know this might be a BAD practice but you could possible try anding 2 signals on two seprate clocks together to get a PWM of 2ns. who cares about the "rules" if it works. then all you care about is the max and min tco of the device

I just created a PLL in a Cyclone IV speed grade 8. With that pll I have a 100mhz clk input and the output is a 50mhz CLK 10% duty cycle. I created the pll with no errors.

I compiled it, with no errors. I am confident that it would work.

I can go down to 4% duty cycle before it starts complaining

you can get a Cyclone iv for around 30$ easy.

just in case you were wondering

These PLL also offer dynamic reconfiguration. So from what i understand about your design it would be easy to implement with a Cyclone IV

go here to learn about dynamic reconfiguration

http://www.altera.com/literature/ug/ug_altpll_reconfig.pdf

sorry to make a lot of posts