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Altera_Forum
Honored Contributor
Honored ContributorFast frequency generation/ modulation
Hi there I am not really familiar with FPGA families and their spped grades etc Is anyone here able to telll me what is the fastest clock signal and PWM signal I could output from a Alte...
Altera_ForumHonored Contributor
Honored ContributorI just created a PLL in a Cyclone IV speed grade 8. With that pll I have a 100mhz clk input and the output is a 50mhz CLK 10% duty cycle. I created the pll with no errors.
I compiled it, with no errors. I am confident that it would work. I can go down to 4% duty cycle before it starts complaining you can get a Cyclone iv for around 30$ easy.
