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Altera_Forum
Honored Contributor
Honored ContributorFast frequency generation/ modulation
Hi there I am not really familiar with FPGA families and their spped grades etc Is anyone here able to telll me what is the fastest clock signal and PWM signal I could output from a Alte...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- 10% of duty cycle at 50MHz would require a 2ns pulse, would a lower end device definitely support that? --- Quote End --- The smallest duty cycle would be a single clock period. Eg. lets say you use a clock frequency of 100MHz, then 10ns is your minimum pulse width. If you need a 2ns pulse width, then you could use an LVDS transceiver operating at 500Mbps. You would need to check the LVDS specifications for the device. The Stratix II devices can definitely generate 2ns pulses. However, 2ns seems like a really short pulse for a PWM operation. What are you trying to do? Cheers, Dave
