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Altera_Forum
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15 years ago

Fail to Boot Software from EPCS16

Hi,

I have made a simple custom system with a EP3C16Q240, EPCS16,SDRAM,an AS connector,a JTAG connector and a 50Mhz system clock in which MSEL[0:2]=[010],VCCIO=3.3V.The SOPC contains a cpu with reset vector=EPCS_controller and exception vector=sdram,an 8k on chip ram,an 8k on rom,an EPCS_controller with base address 0x00000000,a jtag_uart,a system ID,a sdram conytoller,a test_uart,a 8bit pio.

What I want is to write HW and SW into EPCS16 and,after power on,the system can load SW into sdram from EPCS16,and then run the SW automatically.

Now the .sof file .can be written into EPCS16 and work well.But When writing .elf into EPCS16 using IDE's flash programmer the IDE said:

No EPCS layout data - looking for section [EPCS-000000]

Unable to use EPCS device

Leaving target processor paused

After searching the Altera's mysupport and forum I found nothing to solve the "[EPCS-000000]" problem,so I tried to use elf2flash to solve it.I did the following:

1) Convert SOF to Flash

sof2flash --epcs --input=MyNios.sof --output=hw.flash --quiet

2) Convert ELF to Flash

elf2flash --epcs --after=hw.flash --input=MyLed.elf --output=sw.flash --boot=epcs_controller_boot_rom.flash

3) Concatenate

cp hw.flash hw_sw.flash

cat sw.flash >> hw_sw.flash

4) Create HexFile

nios2-elf-objcopy --input-target srec --output-target ihex hw_sw.flash hw_sw.hex

5) Convert hex to jic

quartus ii->file->Convert Programming Files:

Programming file type: JTAG Indirect Configuration File(.jic)

Configuration device: EPCS16

File name: hw_sw.jic

Input files to convert: Flash Loader(EP3C16),Hex_Data(Properties=Absolute addressing,Start Address=0x00000000,hw_sw.hex)

Finally the jic file(hw_sw.jic ) was written into epcs using programmer utility of quartus ii by the JTAG connector.Unfortunately the SW did not work while the HW(.sof ffile) worked well.But when "run as hardware" in IDE the SW worked well even though the SW would not work after cycle powering on the board.

My questions are:

1. What may be the reason leading to "[EPCS-000000]" ?

2. Is there any person who came across the "[EPCS-000000]" and solved it?

3. Are the above 5 steps correct? Had the SW been written into EPCS16 once the jic was programmed ok?

4. Further more why the SW did not work?

Thanks in advance.

Liu Jiangning

14 Replies

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I've got it!

    The problem was not the fpga extra hardware (MSEL and all was ok) nor the epcs_controller in nios.

    The problem was the top-level pin assignements in cyclone III. I was using DATA0, DCLK, nCSO and ASCO signals but they weren't well asigned to fpga's configuration pines.

    Now I can access ecps via nios and i can use flash-programmer.

    Thank you very much for your help.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Have you prove with 'no code at reset' in nios bsp settings?

    --- Quote End ---

    Thanks for the advice. It worked.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    ealonso,

    I'm struggling with this same problem.

    Can you be a bit more specific on your May 6th post? When you write "weren't well asigned to fpga's configuration pines" what do you mean? Do you mean weren't assigned correctly? What assignment did you end up with?

    I have DCLK assigned to pin 12, Data0 assigned to pin 13, nCSO (named sce in the VHDL model) assigned to pin 8, and ASCO (named sco in the vhdl model) assigned to pin 6.

    Thank you for your help so far
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    @ttrickel

    I believe what ealonso meant was that, after he instantiated the epcs_controller inside his FPGA, he has to connect the epcs_controller signals to the top level of his FPGA. He then has to assign those top level FPGA ports to pins using the Pin Planner. He probably meant he wasn't assigning them properly in the Pin Planner.

    Please refer to page 4-3 in Embedded Peripherals IP Users Guide for more information of these steps.