Forum Discussion
Altera_Forum
Honored Contributor
15 years agoealonso,
I'm struggling with this same problem. Can you be a bit more specific on your May 6th post? When you write "weren't well asigned to fpga's configuration pines" what do you mean? Do you mean weren't assigned correctly? What assignment did you end up with? I have DCLK assigned to pin 12, Data0 assigned to pin 13, nCSO (named sce in the VHDL model) assigned to pin 8, and ASCO (named sco in the vhdl model) assigned to pin 6. Thank you for your help so far