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Altera_Forum
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16 years ago

Fail to Boot Software from EPCS16

Hi, I have made a simple custom system with a EP3C16Q240, EPCS16,SDRAM,an AS connector,a JTAG connector and a 50Mhz system clock in which MSEL[0:2]=[010],VCCIO=3.3V.The SOPC contains a cpu with re...
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Altera_Forum
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16 years ago

@ttrickel

I believe what ealonso meant was that, after he instantiated the epcs_controller inside his FPGA, he has to connect the epcs_controller signals to the top level of his FPGA. He then has to assign those top level FPGA ports to pins using the Pin Planner. He probably meant he wasn't assigning them properly in the Pin Planner.

Please refer to page 4-3 in Embedded Peripherals IP Users Guide for more information of these steps.