Forum Discussion
Honored ContributorExport synthesized top-module and import in another project
I am working on a project where different engineers will be developing different modules of a large design completely separately. The design must be entirely bottom-up because the module developers may never know anything about the rest of the design. So, I need the ability to create a project, synthesize it, and export the netlist (along with a stub file). Then, in another project/design I need to import that netlist as a submodule.
I was able to do this easily in Quartus Standard (versions 12-17) by exporting a QXP netlist and importing that netlist in another project. In Quartus Pro 17.0, QXP netlists are no longer supported. I attempted to do the same thing using QDP files, but had no luck. I tried exporting the design as a "partition" but it will not let me export the top-module as a partition (only sub-modules). Export/import "design" does not help here either because when "importing", it seems to assume the design (QDB\) file being imported represents the entire design. So, how can I export a synthesized design from the top-module and import the result (netlist or qdb...) in another project? As a reminder, my use-case involves lower-level designs that will never have any knowledge of the higher-level designs. So, it is not possible to create a full design and designate sub-modules as partitions. Note: while I use the GUI to figure things out, ultimately my projects will be entirely command line, so any Tcl or command-line commands are very helpful (e.g. quartus_syn/quartus_cdb commands/options).17 Replies
Altera_ForumCheck out this online training:
https://www.altera.com/support/training/course/obbdr100.html and this app note: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/tt/tt-intel-fpga-design-reuse.pdf The training is based off of 17.0 while the app note uses 17.1, so the process of creating the root_partition export in the developer project is a little easier (it's in the GUI now). I think you're missing that the root_partition doesn't get imported into the consumer project; it essentially *becomes* the consumer project for the consumer to "fill in" with the internal design in the designated empty partition "hole".- Altera_Forum--- Quote Start --- Check out this online training: https://www.altera.com/support/training/course/obbdr100.html and this app note: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/tt/tt-intel-fpga-design-reuse.pdf The training is based off of 17.0 while the app note uses 17.1, so the process of creating the root_partition export in the developer project is a little easier (it's in the GUI now). I think you're missing that the root_partition doesn't get imported into the consumer project; it essentially *becomes* the consumer project for the consumer to "fill in" with the internal design in the designated empty partition "hole". --- Quote End --- Thank you @sstrell! I will make sure to look through the training material. I have looked through the second link. I guess what confuses is me, is the "it essentially *becomes* the consumer project...". I want to synthesize project B, and generate B.qdb. I also want to synthesize projects C, D, E, F... and create netlists C.qdb, D.qdb, E.qdb, F.qdb. All of these projects will be synthesized before project A exists at all. Finally, project A will be created with its own logic, instantiate modules C, D, E, F..., and import the corresponding netlists. Project A will then be synthesized. Note that this may even be recursive; project A may be just one module in a much larger design. Again all of this is quite straightforward in Quartus Standard using QXP netlists. Maybe I am just misunderstanding your wording (and the wording in the Quartus Pro documentation). Thanks, David
- Altera_Forum
Sorry about the duplicate post.... I did not see my reply in the thread.
I am going through that training class that @strell mentioned. My confusion remains. I want to export my entire project/design as a synthesized netlist (ONLY synthesis)... not a sub-module of my design. How can I do this, if I cannot export the top level of my design as a partition? Do I just use the '--export_design' option to quartus_cdb? I cannot figure out how to do this in the GUI, but like I mentioned before I ultimately need to do this all via command-line or Tcl. The Altera docs and training always export a sub-module as a partition. I want to export my top-level module as a netlist and import it elsewhere as a submodule. And to reiterate, I will only be running synthesis on this module. Fitting and timing will not be run until all submodules have been included in a final design. Thank you, David - Altera_Forum
I am going through that training class that @strell mentioned. My confusion remains. I want to export my entire project/design as a synthesized netlist (ONLY synthesis)... not a sub-module of my design. How can I do this if I cannot export the top level of my design as a partition? Do I just use the '--export_design' option to quartus_cdb (I have not had luck with this yet...)? I cannot figure out how to do this in the GUI, but like I mentioned before I ultimately need to do this all via command-line or Tcl.
The Altera docs and training always export a sub-module as a partition. I want to export my top-level module as a netlist and import it elsewhere as a submodule. And to reiterate, I will only be running synthesis on this module. Fitting and timing will not be run until all submodules have been included in a final design. Thank you, David - Altera_Forum
Try this wording: the developer project is where you create the top-level design that turns into the root_partition. Think of it like swiss cheese: there's a big hole in the middle that will be filled in with the internal function of the design. You then have a consumer project that takes that root_partition where the hole is filled in.
Your project letter names you mention don't designate which project will be the developer project where the root_partition will be designed with multiple holes for the other parts of the design. Once that is done a consumer project gets created from it and the holes are filled in with .qdb files from each person working on a different part of the design. Each of these people will have to honor the Logic Lock region assignments defined in the developer project so that their part of the design is placed in the correct hole in the swiss cheese. You have to create the top-level design and root_partition.qdb in its own project to make all this happen. - Altera_Forum
Thank you again @sstrell. I am not sure which project I would designate as the developer project. At first glance, it seems like I would want the final project (defining the final top-module, peripherals, etc) to be the developer project with the root_partition. But then the fact that the 'consumer' project takes the root_partition and fills in 1 or more holes does not fit my model. Maybe you could help me determine what project(s) should be the developer and consumer?
I have projects A, B, and C. I want to export the entire B and C designs (their top-modules) as netlists. Again, B and C will never have any knowledge of A. A will instantiate the B and C modules and import their netlists. As I mentioned in a previous post, project A might ultimately be a submodule of another larger design. In Quartus Standard, the process is essentially: Compile projects B and C to netlists and create stubs. Instantiate B and C in project A and import the netlists and stubs. Compile project A. This process can repeat recursively if A is a submodule of a larger design or if B and C have submodules. Should the 'developer' project be the final project that results in a bitstream, or is that a 'consumer' project? - Altera_Forum
No, the developer project for periphery reuse is just the top-level I/O and logic designated as part of the top. It is not the final project. The consumer project is the final project with the full design.
Which of A, B, or C has the top-level I/O? That would be the developer project in your scenario. There can't be more than one project with top-level I/O. If there is a project that instantiates A, that is the developer project. It sounds more like you do not want to be exporting and reusing root_partition, that you just want to integrate a number of design partitions into a final project (which would be the consumer project). In that case, you essentially have multiple developer projects (A, B, and C) each providing a .qdb file to add to the "larger design" you mention. That's the "Core Reuse" flow, not Periphery Reuse. - Altera_Forum--- Quote Start --- No, the developer project for periphery reuse is just the top-level I/O and logic designated as part of the top. It is not the final project. The consumer project is the final project with the full design. Which of A, B, or C has the top-level I/O? That would be the developer project in your scenario. There can't be more than one project with top-level I/O. If there is a project that instantiates A, that is the developer project. It sounds more like you do not want to be exporting and reusing root_partition, that you just want to integrate a number of design partitions into a final project (which would be the consumer project). In that case, you essentially have multiple developer projects (A, B, and C) each providing a .qdb file to add to the "larger design" you mention. That's the "Core Reuse" flow, not Periphery Reuse. --- Quote End --- Okay, that helps. So in the "Core Reuse" flow, my problem remains that I want to have developer projects A, B, and C, and I want to compile a QDB and reuse the top module of each of these projects. I have not been able to determine a way to reuse an entire design. I cannot export a design partition of the top module of a project: only sub-modules. Any further advice? Thanks again for all of the help. And sorry for the wordy/confusing replies :D
- Altera_Forum
That's not how design reuse works. You don't reuse the top module from multiple projects because there can only be one top that connects to the I/O. Are you saying that there is no overlap of top-level I/O use between the three projects? If that's the case, the easiest thing would be to create a new top-level design entity (.v or .vhd) that merges the I/O pin use of the three designs and instantiates the three designs then use .qdb files for the submodules for each design. Basically create a top-level wrapper file.
- Altera_Forum--- Quote Start --- That's not how design reuse works. You don't reuse the top module from multiple projects because there can only be one top that connects to the I/O. Are you saying that there is no overlap of top-level I/O use between the three projects? If that's the case, the easiest thing would be to create a new top-level design entity (.v or .vhd) that merges the I/O pin use of the three designs and instantiates the three designs then use .qdb files for the submodules for each design. Basically create a top-level wrapper file. --- Quote End --- Okay.... I do not understand why this is not how design reuse works. This is exactly how I do this with Quartus Standard (and all previous versions of Quartus as well as all other tools I use). The top module of a project is not necessarily the top module of an entire design. There should be some way to synthesize my entire project to a netlist and reuse that netlist elsewhere. Is this possible in Quartus Pro? In the design flow I desire, only the last/final project will touch I/O. For intermediate projects, I just want to generate a netlist for reuse. Thank you for the help, David
