Export synthesized top-module and import in another project

That's not how design reuse works. You don't reuse the top module from multiple projects because there can only be one top that connects to the I/O. Are you saying that there is no overlap of top-level I/O use between the three projects? If that's the case, the easiest thing would be to create a new top-level design entity (.v or .vhd) that merges the I/O pin use of the three designs and instantiates the three designs then use .qdb files for the submodules for each design. Basically create a top-level wrapper file.