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That's not how design reuse works. You don't reuse the top module from multiple projects because there can only be one top that connects to the I/O. Are you saying that there is no overlap of top-level I/O use between the three projects? If that's the case, the easiest thing would be to create a new top-level design entity (.v or .vhd) that merges the I/O pin use of the three designs and instantiates the three designs then use .qdb files for the submodules for each design. Basically create a top-level wrapper file.
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Okay.... I do not understand why this is not how design reuse works. This is exactly how I do this with Quartus Standard (and all previous versions of Quartus as well as all other tools I use). The top module of a project is not necessarily the top module of an entire design. There should be some way to synthesize my entire project to a netlist and reuse that netlist elsewhere. Is this possible in Quartus Pro?
In the design flow I desire, only the last/final project will touch I/O. For intermediate projects, I just want to generate a netlist for reuse.
Thank you for the help,
David
Honored Contributor
