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Check out this online training:
https://www.altera.com/support/training/course/obbdr100.html and this app note:
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/tt/tt-intel-fpga-design-reuse.pdf The training is based off of 17.0 while the app note uses 17.1, so the process of creating the root_partition export in the developer project is a little easier (it's in the GUI now). I think you're missing that the root_partition doesn't get imported into the consumer project; it essentially *becomes* the consumer project for the consumer to "fill in" with the internal design in the designated empty partition "hole".
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Thank you @sstrell! I will make sure to look through the training material. I have looked through the second link.
I guess what confuses is me, is the "it essentially *becomes* the consumer project...". I want to synthesize project B, and generate B.qdb. I also want to synthesize projects C, D, E, F... and create netlists C.qdb, D.qdb, E.qdb, F.qdb. All of these projects will be synthesized
before project A exists at all. Finally, project A will be created with its own logic, instantiate modules C, D, E, F..., and import the corresponding netlists. Project A will then be synthesized. Note that this may even be recursive; project A may be just one module in a much larger design.
Again all of this is quite straightforward in Quartus Standard using QXP netlists. Maybe I am just misunderstanding your wording (and the wording in the Quartus Pro documentation).
Thanks,
David
Honored Contributor
