Honored Contributorsir, i'm using modelsim for simulating my VHDL code.
When i was simulating, i encountered an error. The error statement was as given below: Signal "prior_a0" is type ieee.std_logic_1164.std_logic; expecting type ieee.std_logic_1164.std_logic_vector can u pls help me in trobleshooting this problem.. i'm stuct in between my project because of this error. kind:)y answer
Honored Contributorno, sir. this error was encountered when i was moulding the top level entity
Honored Contributorur signal is of more than one bit.....so u have to define it as
STD_LOGIC_VECTOR(max:min);Honored Contributorsir, the sir is not yet cleared.
so, i'm senting u the source of my top level entity. kinly point out the correction, i will make the corrections pls help, i'm an omly a beginner in this design:confused: ----AUTOPILOT TRANSPORT SYSTEM - TOP LEVEL ENTITY---------- ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity ats_top is port( reset: in std_logic; clk : in std_logic; IrC : in std_logic; IrL : in std_logic; IrR : in std_logic; c : in std_logic_vector(3 downto 0); l : out std_logic_vector(3 downto 0); r: out std_logic_vector(3 downto 0); g: out std_logic_vector(7 downto 0)); end ats_top; architecture arc_ats_top of ats_top is --signal clk: std_logic; signal rst_a0: std_logic; signal rst_a1: std_logic; signal rst_a2: std_logic; signal rst_a3: std_logic; signal rst_x: std_logic_vector(1 downto 0); signal rst_e: std_logic; signal rst_lp: std_logic; signal rst_c: std_logic_vector(3 downto 0); signal rst_r: std_logic_vector(3 downto 0); signal rst_l: std_logic_vector(3 downto 0); signal rst_p: std_logic_vector(3 downto 0); --signal rst_output: std_logic_vector(3 downto 0); ------------------------------------------------------ signal manual_c:std_logic_vector(3 downto 0); signal manual_r:std_logic_vector(3 downto 0); signal manual_l:std_logic_vector(3 downto 0); signal manual_m:std_logic; --signal manual_output:std_logic; ------------------------------------------------------ --signal prior_call_rst:std_logic; signal prior_a0:std_logic; signal prior_a1:std_logic; signal prior_a2:std_logic; signal prior_a3:std_logic; signal prior_e:std_logic; --signal prior_m:std_logic; signal prior_s:std_logic; signal prior_c:std_logic_vector(3 downto 0); --signal prior_call_output: std_logic; ------------------------------------------------------ signal lead_user_rst:std_logic; --signal lead_user_a0:std_logic; --signal lead_user_a1:std_logic; --signal lead_user_a2:std_logic; --signal lead_user_a3:std_logic; --signal lead_user_e:std_logic; --signal lead_user_s:std_logic; signal lead_user_output:std_logic_vector(1 downto 0); signal lead_user_c:std_logic_vector(3 downto 0); --signal lead_user_output: std_logic_vector(1 downto 0); ------------------------------------------------------ --signal map_route_rst: std_logic; signal map_route_x: std_logic_vector(1 downto 0); signal map_route_p: std_logic_vector(3 downto 0); --signal map_route_output: std_logic_vector(3 downto 0); ------------------------------------------------------ --signal path_with_obstacle_rst: std_logic; signal path_with_obstacle_lp: std_logic; signal path_with_obstacle_p: std_logic_vector(3 downto 0); signal path_with_obstacle_IrC: std_logic; signal path_with_obstacle_IrL: std_logic; signal path_with_obstacle_IrR: std_logic; signal path_with_obstacle_a0: std_logic; signal path_with_obstacle_a1: std_logic; signal path_with_obstacle_a2: std_logic; signal path_with_obstacle_a3: std_logic; signal path_with_obstacle_s: std_logic; signal path_with_obstacle_g: std_logic_vector(7 downto 0); signal path_with_obstacle_l: std_logic_vector(3 downto 0); signal path_with_obstacle_r: std_logic_vector(3 downto 0); --signal path_with_obstacle_output: std_logic_vector(3 downto 0); --component system_clock -- port(reset:in std_logic; -- sys_clk: out std_logic); --end component; component rst port(reset: in std_logic; a0: out std_logic; a1: out std_logic; a2: out std_logic; a3: out std_logic; e: out std_logic; s: out std_logic; lp: out std_logic; m: out std_logic; x: out std_logic_vector(1 downto 0); c: out std_logic_vector(3 downto 0); l: out std_logic_vector(3 downto 0); r: out std_logic_vector(3 downto 0); p: out std_logic_vector(3 downto 0)); end component; component manual port(c:in std_logic_vector(3 downto 0); r:out std_logic_vector(3 downto 0); l:out std_logic_vector(3 downto 0); m: out std_logic); end component; component prior port(c: in std_logic_vector(3 downto 0); reset: in std_logic; m: in std_logic; a0: out std_logic; a1: out std_logic; a2: out std_logic; a3: out std_logic; e: out std_logic); end component; component lead_user port(c: in std_logic_vector(3 downto 0); a0: in std_logic_vector(8 : 4); a1: in std_logic_vector(8 : 4); a2: in std_logic_vector(8 : 4); a3: in std_logic_vector(8 : 4); e: in std_logic; s: in std_logic; reset: in std_logic; x: out std_logic_vector(1 downto 0)); end component; component map_route port(clk: in std_logic; reset:in std_logic; x: in std_logic_vector(1 downto 0); p: out std_logic_vector( 3 downto 0)); end component; component path_with_obstacle port(reset: in std_logic; clk: in std_logic; lp: in std_logic; IrC: in std_logic; IrL: in std_logic; IrR: in std_logic; p: in std_logic_vector(3 downto 0); s: out std_logic; a0: out std_logic; a1: out std_logic; a2: out std_logic; a3: out std_logic; l: out std_logic_vector(3 downto 0); r: out std_logic_vector(3 downto 0); g: out std_logic_vector(7 downto 0)); end component; begin lead_user_c <= prior_c; --lead_user_a0 <= prior_a0; --lead_user_a1 <= prior_a1; --lead_user_a2 <= prior_a2; --lead_user_a3 <= prior_a3; -- lead_user_e <= prior_e; --lead_user_s <= path_with_obstacle_s; map_route_x <= lead_user_output; path_with_obstacle_p <= map_route_p; prior_a0 <= path_with_obstacle_a0; prior_a1 <= path_with_obstacle_a1; prior_a2 <= path_with_obstacle_a2; prior_a3 <= path_with_obstacle_a3; prior_s <= path_with_obstacle_s; -- syc : system_clock port map(reset,sys_clk); rest: rst port map(clk,rst_a0,rst_a1,rst_a2,rst_a3); man : manual port map(manual_l,manual_r,manual_c); pri : prior port map(prior_c,prior_a0,prior_a1,prior_a2,prior_a3,prior_e); lead : lead_user port map(prior_a0,prior_a1,prior_a2,prior_a3, prior_e,prior_s,lead_user_c,lead_user_output); mapr : map_route port map(clk,lead_user_output,map_route_p); motor : path_with_obstacle port map(clk,map_route_p,path_with_obstacle_lp,path_with_obstacle_IrC,path_with_obstacle_IrL,path_with_obstacle_IrR,path_with_obstacle_r,path_with_obstacle_l,path_with_obstacle_a0,path_with_obstacle_a1,path_with_obstacle_a2,path_with_obstacle_a3,path_with_obstacle_s,path_with_obstacle_g); end arc_ats_top;Honored Contributorsir, don't ignore this sir. ther is no one to guide me.
i'm doing all by myself by referring to various text books and articles in the internet. kindly reply...plsHonored ContributorModelSIm error messages also tell you which instruction causes the error. Please provide complete information!
I guess the error is in component instantiation. Unfortunately, you're using positional association, which is easily causing confusion. I suggest to use named assosiation instead. I fear, there are more errors with port maps in your code. Simply consider, that each port expression must have the same type as the respective port.Honored ContributorHi,
--- Quote Start --- lead : lead_user port map(prior_a0,prior_a1,prior_a2,prior_a3, prior_e,prior_s,lead_user_c,lead_user_output); You are mapping ports by position, and not by name. here prior_a0 is mapped to port c on lead_user component which have different types. I suggest you to employ port mapping by name like --- Quote Start --- lead : lead_user port map( c => ...,a0 => ... ,a1 => .... ...); --- Quote End --- I think, you are confused about what you want exactly to do. You want to connect a single signal to a "composed" signal. Are you sure about your design ? It's very important. vhdl just describes a logical circuit.Honored Contributorsir, the sir is not yet cleared.
so, i'm senting u the source of my top level entity. kinly point out the correction, i will make the corrections pls help, i'm an omly a beginner in this design:confused: ----AUTOPILOT TRANSPORT SYSTEM - TOP LEVEL ENTITY---------- ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity ats_top is port( reset: in std_logic; clk : in std_logic; IrC : in std_logic; IrL : in std_logic; IrR : in std_logic; c : in std_logic_vector(3 downto 0); l : out std_logic_vector(3 downto 0); r: out std_logic_vector(3 downto 0); g: out std_logic_vector(7 downto 0)); end ats_top; architecture arc_ats_top of ats_top is --signal clk: std_logic; signal rst_a0: std_logic; signal rst_a1: std_logic; signal rst_a2: std_logic; signal rst_a3: std_logic; signal rst_x: std_logic_vector(1 downto 0); signal rst_e: std_logic; signal rst_lp: std_logic; signal rst_c: std_logic_vector(3 downto 0); signal rst_r: std_logic_vector(3 downto 0); signal rst_l: std_logic_vector(3 downto 0); signal rst_p: std_logic_vector(3 downto 0); --signal rst_output: std_logic_vector(3 downto 0); ------------------------------------------------------ signal manual_c:std_logic_vector(3 downto 0); signal manual_r:std_logic_vector(3 downto 0); signal manual_l:std_logic_vector(3 downto 0); signal manual_m:std_logic; --signal manual_output:std_logic; ------------------------------------------------------ --signal prior_call_rst:std_logic; signal prior_a0:std_logic; signal prior_a1:std_logic; signal prior_a2:std_logic; signal prior_a3:std_logic; signal prior_e:std_logic; --signal prior_m:std_logic; signal prior_s:std_logic; signal prior_c:std_logic_vector(3 downto 0); --signal prior_call_output: std_logic; ------------------------------------------------------ signal lead_user_rst:std_logic; --signal lead_user_a0:std_logic; --signal lead_user_a1:std_logic; --signal lead_user_a2:std_logic; --signal lead_user_a3:std_logic; --signal lead_user_e:std_logic; --signal lead_user_s:std_logic; signal lead_user_output:std_logic_vector(1 downto 0); signal lead_user_c:std_logic_vector(3 downto 0); --signal lead_user_output: std_logic_vector(1 downto 0); ------------------------------------------------------ --signal map_route_rst: std_logic; signal map_route_x: std_logic_vector(1 downto 0); signal map_route_p: std_logic_vector(3 downto 0); --signal map_route_output: std_logic_vector(3 downto 0); ------------------------------------------------------ --signal path_with_obstacle_rst: std_logic; signal path_with_obstacle_lp: std_logic; signal path_with_obstacle_p: std_logic_vector(3 downto 0); signal path_with_obstacle_IrC: std_logic; signal path_with_obstacle_IrL: std_logic; signal path_with_obstacle_IrR: std_logic; signal path_with_obstacle_a0: std_logic; signal path_with_obstacle_a1: std_logic; signal path_with_obstacle_a2: std_logic; signal path_with_obstacle_a3: std_logic; signal path_with_obstacle_s: std_logic; signal path_with_obstacle_g: std_logic_vector(7 downto 0); signal path_with_obstacle_l: std_logic_vector(3 downto 0); signal path_with_obstacle_r: std_logic_vector(3 downto 0); --signal path_with_obstacle_output: std_logic_vector(3 downto 0); --component system_clock -- port(reset:in std_logic; -- sys_clk: out std_logic); --end component; component rst port(reset: in std_logic; a0: out std_logic; a1: out std_logic; a2: out std_logic; a3: out std_logic; e: out std_logic; s: out std_logic; lp: out std_logic; m: out std_logic; x: out std_logic_vector(1 downto 0); c: out std_logic_vector(3 downto 0); l: out std_logic_vector(3 downto 0); r: out std_logic_vector(3 downto 0); p: out std_logic_vector(3 downto 0)); end component; component manual port(c:in std_logic_vector(3 downto 0); r:out std_logic_vector(3 downto 0); l:out std_logic_vector(3 downto 0); m: out std_logic); end component; component prior port(c: in std_logic_vector(3 downto 0); reset: in std_logic; m: in std_logic; a0: out std_logic; a1: out std_logic; a2: out std_logic; a3: out std_logic; e: out std_logic); end component; component lead_user port(c: in std_logic_vector(3 downto 0); a0: in std_logic_vector(8 : 4); a1: in std_logic_vector(8 : 4); a2: in std_logic_vector(8 : 4); a3: in std_logic_vector(8 : 4); e: in std_logic; s: in std_logic; reset: in std_logic; x: out std_logic_vector(1 downto 0)); end component; component map_route port(clk: in std_logic; reset:in std_logic; x: in std_logic_vector(1 downto 0); p: out std_logic_vector( 3 downto 0)); end component; component path_with_obstacle port(reset: in std_logic; clk: in std_logic; lp: in std_logic; IrC: in std_logic; IrL: in std_logic; IrR: in std_logic; p: in std_logic_vector(3 downto 0); s: out std_logic; a0: out std_logic; a1: out std_logic; a2: out std_logic; a3: out std_logic; l: out std_logic_vector(3 downto 0); r: out std_logic_vector(3 downto 0); g: out std_logic_vector(7 downto 0)); end component; begin lead_user_c <= prior_c; --lead_user_a0 <= prior_a0; --lead_user_a1 <= prior_a1; --lead_user_a2 <= prior_a2; --lead_user_a3 <= prior_a3; -- lead_user_e <= prior_e; --lead_user_s <= path_with_obstacle_s; map_route_x <= lead_user_output; path_with_obstacle_p <= map_route_p; prior_a0 <= path_with_obstacle_a0; prior_a1 <= path_with_obstacle_a1; prior_a2 <= path_with_obstacle_a2; prior_a3 <= path_with_obstacle_a3; prior_s <= path_with_obstacle_s; -- syc : system_clock port map(reset,sys_clk); rest: rst port map(clk,rst_a0,rst_a1,rst_a2,rst_a3); man : manual port map(manual_l,manual_r,manual_c); pri : prior port map(prior_c,prior_a0,prior_a1,prior_a2,prior_a3,prior_e); lead : lead_user port map(prior_a0,prior_a1,prior_a2,prior_a3, prior_e,prior_s,lead_user_c,lead_user_output); mapr : map_route port map(clk,lead_user_output,map_route_p); motor : path_with_obstacle port map(clk,map_route_p,path_with_obstacle_lp,path_with_obstacle_IrC,path_with_obstacle_IrL,path_with_obstacle_IrR,path_with_obstacle_r,path_with_obstacle_l,path_with_obstacle_a0,path_with_obstacle_a1,path_with_obstacle_a2,path_with_obstacle_a3,path_with_obstacle_s,path_with_obstacle_g); end arc_ats_top; --- Quote End ---Honored ContributorHey Varun...I m trying to give u the solution....
This is the part of ur code U had send me....... --------------------------------------------------- component lead_user port(c: in std_logic_vector(3 downto 0); a0: in std_logic_vector(8 : 4); a1: in std_logic_vector(8 : 4); a2: in std_logic_vector(8 : 4); a3: in std_logic_vector(8 : 4); e: in std_logic; s: in std_logic; reset: in std_logic; x: out std_logic_vector(1 downto 0)); end component; --------------------------------------------------------- and this is the line of code where u r mapping the port.... -------------------------------------------------------- lead : lead_user port map(prior_a0,prior_a1,prior_a2,prior_a3, prior_e,prior_s,lead_user_c,lead_user_output); ------------------------------------------------ Here u r using positional mapping of ports......... So, prior_a0 will be assigned to C, prior_a1 will be assigned to a0, prior_a2 will be assigned to a1, prior_a3 will be assigned to a2, and so forth...... I hope u got this point........ And The prior_a0 which is a single bit value which is assigned to a0: in std_logic_vector(8 : 4); a multi bit value.......... So after proper mapping of ports....u should match the type of ports alsoHonored Contributorsir thanks for ur guidance. with ur guidance i had solved some of the problems. but still some errors exist. i'm sending both the error report and modified codes.
kindly help me to correct my mistakes \\error report\\ Signal "lead_user_output" is type ieee.std_logic_1164.std_logic; expecting type ieee.std_logic_1164.std_logic_vector length of formal x is 2, length of actual is 4 file:///C:/Documents%20and%20Settings/ScORP/Desktop/ERROR.JPG \\modified code\\ ------------------------------------------------------------ -----AUTOPILOT TRANSPORT SYSTEM - TOP LEVEL ENTITY---------- ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity ats_top is port( reset: in std_logic; clk : in std_logic; IrC : in std_logic; IrL : in std_logic; IrR : in std_logic; c : in std_logic_vector(3 downto 0); l : out std_logic_vector(3 downto 0); r: out std_logic_vector(3 downto 0); g: out std_logic_vector(7 downto 0)); end ats_top; architecture arc_ats_top of ats_top is --signal clk: std_logic; signal rst_p: std_logic_vector(3 downto 0); signal rst_a0: std_logic; signal rst_a1: std_logic; signal rst_a2: std_logic; signal rst_a3: std_logic; signal rst_x: std_logic_vector(1 downto 0); signal rst_e: std_logic; signal rst_lp: std_logic; signal rst_c: std_logic_vector(3 downto 0); signal rst_r: std_logic_vector(3 downto 0); signal rst_l: std_logic_vector(3 downto 0); signal rst_m: std_logic; --signal rst_output: std_logic_vector(3 downto 0); ------------------------------------------------------ signal manual_c:std_logic_vector(3 downto 0); signal manual_r:std_logic_vector(3 downto 0); signal manual_l:std_logic_vector(3 downto 0); signal manual_m:std_logic; --signal manual_output:std_logic; ------------------------------------------------------ --signal prior_call_rst:std_logic; signal prior_a0:std_logic; signal prior_a1:std_logic; signal prior_a2:std_logic; signal prior_a3:std_logic; signal prior_e:std_logic; --signal prior_m:std_logic; signal prior_s:std_logic; signal prior_c:std_logic_vector(3 downto 0); --signal prior_call_output: std_logic; ------------------------------------------------------ signal lead_user_rst:std_logic; --signal lead_user_a0:std_logic; --signal lead_user_a1:std_logic; --signal lead_user_a2:std_logic; --signal lead_user_a3:std_logic; --signal lead_user_e:std_logic; --signal lead_user_s:std_logic; signal lead_user_c:std_logic_vector(3 downto 0); signal lead_user_x:std_logic_vector(1 downto 0); signal lead_user_output: std_logic_vector(1 downto 0); ------------------------------------------------------ --signal map_route_rst: std_logic; signal map_route_x: std_logic_vector(1 downto 0); signal map_route_p: std_logic_vector(3 downto 0); --signal map_route_output: std_logic_vector(3 downto 0); ------------------------------------------------------ --signal path_with_obstacle_rst: std_logic; signal path_with_obstacle_lp: std_logic; signal path_with_obstacle_p: std_logic_vector(3 downto 0); signal path_with_obstacle_IrC: std_logic; signal path_with_obstacle_IrL: std_logic; signal path_with_obstacle_IrR: std_logic; signal path_with_obstacle_a0: std_logic; signal path_with_obstacle_a1: std_logic; signal path_with_obstacle_a2: std_logic; signal path_with_obstacle_a3: std_logic; signal path_with_obstacle_s: std_logic; signal path_with_obstacle_g: std_logic_vector(7 downto 0); signal path_with_obstacle_l: std_logic_vector(3 downto 0); signal path_with_obstacle_r: std_logic_vector(3 downto 0); --signal path_with_obstacle_output: std_logic_vector(3 downto 0); --component system_clock -- port(reset:in std_logic; -- sys_clk: out std_logic); --end component; component rst port(reset: in std_logic; a0: out std_logic; a1: out std_logic; a2: out std_logic; a3: out std_logic; e: out std_logic; s: out std_logic; lp: out std_logic; m: out std_logic; x: out std_logic_vector(1 downto 0); c: out std_logic_vector(3 downto 0); l: out std_logic_vector(3 downto 0); r: out std_logic_vector(3 downto 0); p: out std_logic_vector(3 downto 0)); end component; component manual port(c:in std_logic_vector(3 downto 0); r:out std_logic_vector(3 downto 0); l:out std_logic_vector(3 downto 0); m: out std_logic); end component; component prior port(c: in std_logic_vector(3 downto 0); reset: in std_logic; m: in std_logic; a0: out std_logic; a1: out std_logic; a2: out std_logic; a3: out std_logic; e: out std_logic); end component; component lead_user port(c: in std_logic_vector(3 downto 0); a0: in std_logic; a1: in std_logic; a2: in std_logic; a3: in std_logic; e: in std_logic; s: in std_logic; reset: in std_logic; x: out std_logic_vector(1 downto 0)); end component; component map_route port(clk: in std_logic; reset:in std_logic; x: in std_logic_vector(1 downto 0); p: out std_logic_vector( 3 downto 0)); end component; component path_with_obstacle port(reset: in std_logic; clk: in std_logic; lp: in std_logic; IrC: in std_logic; IrL: in std_logic; IrR: in std_logic; p: in std_logic_vector(3 downto 0); s: out std_logic; a0: out std_logic; a1: out std_logic; a2: out std_logic; a3: out std_logic; l: out std_logic_vector(3 downto 0); r: out std_logic_vector(3 downto 0); g: out std_logic_vector(7 downto 0)); end component; begin --lead_user_c <= prior_c; --lead_user_a0 <= prior_a0; --lead_user_a1 <= prior_a1; --lead_user_a2 <= prior_a2; --lead_user_a3 <= prior_a3; -- lead_user_e <= prior_e; --lead_user_s <= path_with_obstacle_s; --map_route_x <= lead_user_output; --path_with_obstacle_p <= map_route_p; --prior_a0 <= path_with_obstacle_a0; -- prior_a1 <= path_with_obstacle_a1; -- prior_a2 <= path_with_obstacle_a2; -- prior_a3 <= path_with_obstacle_a3; -- prior_s <= path_with_obstacle_s; lead_user_x <= lead_user_output; -- syc : system_clock port map(reset,sys_clk); rest: rst port map(clk,rst_a0,rst_a1,rst_a2,rst_a3); man : manual port map(manual_l,manual_r,manual_c); pri : prior port map(prior_c,manual_m,prior_a0,prior_a1,prior_a2,prior_a3,prior_e); lead : lead_user port map(lead_user_c,prior_a0,prior_a1,prior_a2,prior_a3, prior_e,prior_s,lead_user_output); mapr : map_route port map(clk,lead_user_output,map_route_p); motor : path_with_obstacle port map(clk,path_with_obstacle_lp,path_with_obstacle_IrC,path_with_obstacle_IrL,path_with_obstacle_IrR,map_route_p,path_with_obstacle_s,path_with_obstacle_a0,path_with_obstacle_a1,path_with_obstacle_a2,path_with_obstacle_a3,path_with_obstacle_l,path_with_obstacle_r,path_with_obstacle_g); end arc_ats_top;Honored Contributorsir, i have sorted the errors. really thanks for ur guidance and help.
i'm sending the corrected code . thank u.................. ------------------------------------------------------------ -----AUTOPILOT TRANSPORT SYSTEM - TOP LEVEL ENTITY---------- ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity ats_top is port( reset: in std_logic; clk : in std_logic; IrC : in std_logic; IrL : in std_logic; IrR : in std_logic; c : in std_logic_vector(3 downto 0); l : out std_logic_vector(3 downto 0); r: out std_logic_vector(3 downto 0); g: out std_logic_vector(7 downto 0)); end ats_top; architecture arc_ats_top of ats_top is --signal clk: std_logic; signal rst_a0: std_logic; signal rst_a1: std_logic; signal rst_a2: std_logic; signal rst_a3: std_logic; signal rst_e: std_logic; signal rst_x: std_logic_vector(1 downto 0); signal rst_lp: std_logic; signal rst_c: std_logic_vector(3 downto 0); signal rst_r: std_logic_vector(3 downto 0); signal rst_l: std_logic_vector(3 downto 0); signal rst_m: std_logic; signal rst_p: std_logic_vector(3 downto 0); --signal rst_output: std_logic_vector(3 downto 0); ------------------------------------------------------ signal manual_c:std_logic_vector(3 downto 0); signal manual_r:std_logic_vector(3 downto 0); signal manual_l:std_logic_vector(3 downto 0); signal manual_m:std_logic; --signal manual_output:std_logic; ------------------------------------------------------ --signal prior_call_rst:std_logic; signal prior_a0:std_logic; signal prior_a1:std_logic; signal prior_a2:std_logic; signal prior_a3:std_logic; signal prior_e:std_logic; --signal prior_m:std_logic; signal prior_s:std_logic; signal prior_c:std_logic_vector(3 downto 0); --signal prior_call_output: std_logic; ------------------------------------------------------ signal lead_users_rst:std_logic; --signal lead_user_a0:std_logic; --signal lead_user_a1:std_logic; --signal lead_user_a2:std_logic; --signal lead_user_a3:std_logic; --signal lead_user_e:std_logic; --signal lead_user_s:std_logic; signal lead_users_x:std_logic_vector(1 downto 0); signal lead_users_c:std_logic_vector(3 downto 0); signal lead_users_output: std_logic_vector(1 downto 0); ------------------------------------------------------ --signal map_route_rst: std_logic; signal map_route2_x: std_logic_vector(1 downto 0); signal map_route2_p: std_logic_vector(3 downto 0); --signal map_route_output: std_logic_vector(3 downto 0); ------------------------------------------------------ --signal path_with_obstacle_rst: std_logic; signal path_with_obstacle_lp: std_logic; signal path_with_obstacle_p: std_logic_vector(3 downto 0); signal path_with_obstacle_IrC: std_logic; signal path_with_obstacle_IrL: std_logic; signal path_with_obstacle_IrR: std_logic; signal path_with_obstacle_a0: std_logic; signal path_with_obstacle_a1: std_logic; signal path_with_obstacle_a2: std_logic; signal path_with_obstacle_a3: std_logic; signal path_with_obstacle_s: std_logic; signal path_with_obstacle_g: std_logic_vector(7 downto 0); signal path_with_obstacle_l: std_logic_vector(3 downto 0); signal path_with_obstacle_r: std_logic_vector(3 downto 0); --signal path_with_obstacle_output: std_logic_vector(3 downto 0); --component system_clock -- port(reset:in std_logic; -- sys_clk: out std_logic); --end component; component rst port(reset: in std_logic; a0: out std_logic; a1: out std_logic; a2: out std_logic; a3: out std_logic; e: out std_logic; x: out std_logic_vector(1 downto 0); lp: out std_logic; c: out std_logic_vector(3 downto 0); r: out std_logic_vector(3 downto 0); l: out std_logic_vector(3 downto 0); m: out std_logic; p: out std_logic_vector(3 downto 0)); end component; component manual port(c:in std_logic_vector(3 downto 0); r:out std_logic_vector(3 downto 0); l:out std_logic_vector(3 downto 0); m: out std_logic); end component; component prior port(c: in std_logic_vector(3 downto 0); m: in std_logic; a0: out std_logic; a1: out std_logic; a2: out std_logic; a3: out std_logic; e: out std_logic); end component; component lead_users port(c: in std_logic_vector(3 downto 0); a0: in std_logic; a1: in std_logic; a2: in std_logic; a3: in std_logic; e: in std_logic; s: in std_logic; x: out std_logic_vector(1 downto 0)); end component; component map_route2 port(clk: in std_logic; x: in std_logic_vector(1 downto 0); p: out std_logic_vector( 3 downto 0)); end component; component path_with_obstacle port( clk: in std_logic; lp: in std_logic; IrC: in std_logic; IrL: in std_logic; IrR: in std_logic; p: in std_logic_vector(3 downto 0); s: out std_logic; a0: out std_logic; a1: out std_logic; a2: out std_logic; a3: out std_logic; l: out std_logic_vector(3 downto 0); r: out std_logic_vector(3 downto 0); g: out std_logic_vector(7 downto 0)); end component; begin --lead_user_c <= prior_c; --lead_user_a0 <= prior_a0; --lead_user_a1 <= prior_a1; --lead_user_a2 <= prior_a2; --lead_user_a3 <= prior_a3; -- lead_user_e <= prior_e; --lead_user_s <= path_with_obstacle_s; --map_route_x <= lead_user_output; --path_with_obstacle_p <= map_route_p; --prior_a0 <= path_with_obstacle_a0; -- prior_a1 <= path_with_obstacle_a1; -- prior_a2 <= path_with_obstacle_a2; -- prior_a3 <= path_with_obstacle_a3; -- prior_s <= path_with_obstacle_s; -- lead_user_x <= lead_user_output; -- syc : system_clock port map(reset,sys_clk); rest: rst port map(clk,rst_a0,rst_a1,rst_a2,rst_a3,rst_e,rst_x,rst_lp,rst_c,rst_r,rst_l,rst_m,rst_p); man : manual port map(manual_l,manual_r,manual_c); pri : prior port map(prior_c,manual_m,prior_a0,prior_a1,prior_a2,prior_a3,prior_e); lead : lead_users port map(lead_users_c,prior_a0,prior_a1,prior_a2,prior_a3, prior_e,prior_s,lead_users_output); mapr : map_route2 port map(clk,lead_users_output,map_route2_p); motor : path_with_obstacle port map(clk,path_with_obstacle_lp,path_with_obstacle_IrC,path_with_obstacle_IrL,path_with_obstacle_IrR,map_route2_p,path_with_obstacle_s,path_with_obstacle_a0,path_with_obstacle_a1,path_with_obstacle_a2,path_with_obstacle_a3,path_with_obstacle_l,path_with_obstacle_r,path_with_obstacle_g); end arc_ats_top;
