error in compiling VHDL CODE

Hi,

--- Quote Start ---

lead : lead_user port map(prior_a0,prior_a1,prior_a2,prior_a3, prior_e,prior_s,lead_user_c,lead_user_output);

You are mapping ports by position, and not by name. here prior_a0 is mapped to port c on lead_user component which have different types.

I suggest you to employ port mapping by name like

--- Quote Start ---

lead : lead_user port map( c => ...,a0 => ... ,a1 => .... ...);

--- Quote End ---

I think, you are confused about what you want exactly to do. You want to connect a single signal to a "composed" signal.

Are you sure about your design ? It's very important.

vhdl just describes a logical circuit.