error in compiling VHDL CODE

sir thanks for ur guidance. with ur guidance i had solved some of the problems. but still some errors exist. i'm sending both the error report and modified codes.

kindly help me to correct my mistakes

\\error report\\

Signal "lead_user_output" is type ieee.std_logic_1164.std_logic; expecting type ieee.std_logic_1164.std_logic_vector

length of formal x is 2, length of actual is 4

file:///C:/Documents%20and%20Settings/ScORP/Desktop/ERROR.JPG

\\modified code\\

------------------------------------------------------------

-----AUTOPILOT TRANSPORT SYSTEM - TOP LEVEL ENTITY----------

------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

entity ats_top is

port( reset: in std_logic;

clk : in std_logic;

IrC : in std_logic;

IrL : in std_logic;

IrR : in std_logic;

c : in std_logic_vector(3 downto 0);

l : out std_logic_vector(3 downto 0);

r: out std_logic_vector(3 downto 0);

g: out std_logic_vector(7 downto 0));

end ats_top;

architecture arc_ats_top of ats_top is

--signal clk: std_logic;

signal rst_p: std_logic_vector(3 downto 0);

signal rst_a0: std_logic;

signal rst_a1: std_logic;

signal rst_a2: std_logic;

signal rst_a3: std_logic;

signal rst_x: std_logic_vector(1 downto 0);

signal rst_e: std_logic;

signal rst_lp: std_logic;

signal rst_c: std_logic_vector(3 downto 0);

signal rst_r: std_logic_vector(3 downto 0);

signal rst_l: std_logic_vector(3 downto 0);

signal rst_m: std_logic;

--signal rst_output: std_logic_vector(3 downto 0);

------------------------------------------------------

signal manual_c:std_logic_vector(3 downto 0);

signal manual_r:std_logic_vector(3 downto 0);

signal manual_l:std_logic_vector(3 downto 0);

signal manual_m:std_logic;

--signal manual_output:std_logic;

------------------------------------------------------

--signal prior_call_rst:std_logic;

signal prior_a0:std_logic;

signal prior_a1:std_logic;

signal prior_a2:std_logic;

signal prior_a3:std_logic;

signal prior_e:std_logic;

--signal prior_m:std_logic;

signal prior_s:std_logic;

signal prior_c:std_logic_vector(3 downto 0);

--signal prior_call_output: std_logic;

------------------------------------------------------

signal lead_user_rst:std_logic;

--signal lead_user_a0:std_logic;

--signal lead_user_a1:std_logic;

--signal lead_user_a2:std_logic;

--signal lead_user_a3:std_logic;

--signal lead_user_e:std_logic;

--signal lead_user_s:std_logic;

signal lead_user_c:std_logic_vector(3 downto 0);

signal lead_user_x:std_logic_vector(1 downto 0);

signal lead_user_output: std_logic_vector(1 downto 0);

------------------------------------------------------

--signal map_route_rst: std_logic;

signal map_route_x: std_logic_vector(1 downto 0);

signal map_route_p: std_logic_vector(3 downto 0);

--signal map_route_output: std_logic_vector(3 downto 0);

------------------------------------------------------

--signal path_with_obstacle_rst: std_logic;

signal path_with_obstacle_lp: std_logic;

signal path_with_obstacle_p: std_logic_vector(3 downto 0);

signal path_with_obstacle_IrC: std_logic;

signal path_with_obstacle_IrL: std_logic;

signal path_with_obstacle_IrR: std_logic;

signal path_with_obstacle_a0: std_logic;

signal path_with_obstacle_a1: std_logic;

signal path_with_obstacle_a2: std_logic;

signal path_with_obstacle_a3: std_logic;

signal path_with_obstacle_s: std_logic;

signal path_with_obstacle_g: std_logic_vector(7 downto 0);

signal path_with_obstacle_l: std_logic_vector(3 downto 0);

signal path_with_obstacle_r: std_logic_vector(3 downto 0);

--signal path_with_obstacle_output: std_logic_vector(3 downto 0);

--component system_clock

-- port(reset:in std_logic;

-- sys_clk: out std_logic);

--end component;

component rst

port(reset: in std_logic;

a0: out std_logic;

a1: out std_logic;

a2: out std_logic;

a3: out std_logic;

e: out std_logic;

s: out std_logic;

lp: out std_logic;

m: out std_logic;

x: out std_logic_vector(1 downto 0);

c: out std_logic_vector(3 downto 0);

l: out std_logic_vector(3 downto 0);

r: out std_logic_vector(3 downto 0);

p: out std_logic_vector(3 downto 0));

end component;

component manual

port(c:in std_logic_vector(3 downto 0);

r:out std_logic_vector(3 downto 0);

l:out std_logic_vector(3 downto 0);

m: out std_logic);

end component;

component prior

port(c: in std_logic_vector(3 downto 0);

reset: in std_logic;

m: in std_logic;

a0: out std_logic;

a1: out std_logic;

a2: out std_logic;

a3: out std_logic;

e: out std_logic);

end component;

component lead_user

port(c: in std_logic_vector(3 downto 0);

a0: in std_logic;

a1: in std_logic;

a2: in std_logic;

a3: in std_logic;

e: in std_logic;

s: in std_logic;

reset: in std_logic;

x: out std_logic_vector(1 downto 0));

end component;

component map_route

port(clk: in std_logic;

reset:in std_logic;

x: in std_logic_vector(1 downto 0);

p: out std_logic_vector( 3 downto 0));

end component;

component path_with_obstacle

port(reset: in std_logic;

clk: in std_logic;

lp: in std_logic;

IrC: in std_logic;

IrL: in std_logic;

IrR: in std_logic;

p: in std_logic_vector(3 downto 0);

s: out std_logic;

a0: out std_logic;

a1: out std_logic;

a2: out std_logic;

a3: out std_logic;

l: out std_logic_vector(3 downto 0);

r: out std_logic_vector(3 downto 0);

g: out std_logic_vector(7 downto 0));

end component;

begin

--lead_user_c <= prior_c;

--lead_user_a0 <= prior_a0;

--lead_user_a1 <= prior_a1;

--lead_user_a2 <= prior_a2;

--lead_user_a3 <= prior_a3;

-- lead_user_e <= prior_e;

--lead_user_s <= path_with_obstacle_s;

--map_route_x <= lead_user_output;

--path_with_obstacle_p <= map_route_p;

--prior_a0 <= path_with_obstacle_a0;

-- prior_a1 <= path_with_obstacle_a1;

-- prior_a2 <= path_with_obstacle_a2;

-- prior_a3 <= path_with_obstacle_a3;

-- prior_s <= path_with_obstacle_s;

lead_user_x <= lead_user_output;

-- syc : system_clock port map(reset,sys_clk);

rest: rst port map(clk,rst_a0,rst_a1,rst_a2,rst_a3);

man : manual port map(manual_l,manual_r,manual_c);

pri : prior port map(prior_c,manual_m,prior_a0,prior_a1,prior_a2,prior_a3,prior_e);

lead : lead_user port map(lead_user_c,prior_a0,prior_a1,prior_a2,prior_a3, prior_e,prior_s,lead_user_output);

mapr : map_route port map(clk,lead_user_output,map_route_p);

motor : path_with_obstacle port map(clk,path_with_obstacle_lp,path_with_obstacle_IrC,path_with_obstacle_IrL,path_with_obstacle_IrR,map_route_p,path_with_obstacle_s,path_with_obstacle_a0,path_with_obstacle_a1,path_with_obstacle_a2,path_with_obstacle_a3,path_with_obstacle_l,path_with_obstacle_r,path_with_obstacle_g);

end arc_ats_top;