Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

error in compiling VHDL CODE

sir, i'm using modelsim for simulating my VHDL code. When i was simulating, i encountered an error. The error statement was as given below: Signal "prior_a0" is type ieee.std_logic_1164.std_logi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

ModelSIm error messages also tell you which instruction causes the error. Please provide complete information!

I guess the error is in component instantiation. Unfortunately, you're using positional association, which is easily causing confusion. I suggest to use named assosiation instead. I fear, there are more errors with port maps in your code. Simply consider, that each port expression must have the same type as the respective port.