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Altera_Forum's avatar
Altera_Forum
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17 years ago

error in compiling VHDL CODE

sir, i'm using modelsim for simulating my VHDL code. When i was simulating, i encountered an error. The error statement was as given below: Signal "prior_a0" is type ieee.std_logic_1164.std_logi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

no, sir. this error was encountered when i was moulding the top level entity