error in compiling VHDL CODE

Hey Varun...I m trying to give u the solution....

This is the part of ur code U had send me.......

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component lead_user

port(c: in std_logic_vector(3 downto 0);

a0: in std_logic_vector(8 : 4);

a1: in std_logic_vector(8 : 4);

a2: in std_logic_vector(8 : 4);

a3: in std_logic_vector(8 : 4);

e: in std_logic;

s: in std_logic;

reset: in std_logic;

x: out std_logic_vector(1 downto 0));

end component;

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and this is the line of code where u r mapping the port....

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lead : lead_user port map(prior_a0,prior_a1,prior_a2,prior_a3, prior_e,prior_s,lead_user_c,lead_user_output);

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Here u r using positional mapping of ports.........

So,

prior_a0 will be assigned to C,

prior_a1 will be assigned to a0,

prior_a2 will be assigned to a1,

prior_a3 will be assigned to a2,

and so forth......

I hope u got this point........

And The prior_a0 which is a single bit value which is assigned to

a0: in std_logic_vector(8 : 4); a multi bit value..........

So after proper mapping of ports....u should match the type of ports also