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Altera_Forum's avatar
Altera_Forum
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10 years ago

error: expression is not constant

Hi,

My code is as followed: 

signal cnt_clks                       : natural range 0 to 300;
...
...
cnt_clks        <= conv_integer(unsigned(time)) * 25;                    
 
 process(clk_50, reset)
    begin
        if reset = '1' then
            enc_delay       <= (others => '0');
            enc_delay_in    <= '0';
        elsif rising_edge(clk_50) then
            enc_delay(cnt_clks downto 0)     <= enc_delay((cnt_clks -1) downto 0) & enc_in(1);    
            enc_delay_in                     <= enc_delay(cnt_clks);
        end if;
    end process;

Modelsim compiles it with no problem. Quartus shows the 'Expression is not constant' error (I'm using Quartus 15). How can I overcome that?

I tried defining cnt_clks as Integer, no luck.

Roy

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    what is definition for enc_delay. Hope it declared properly for at least 300 bits long. The size should be greater then maximum value of {cnt_clks} 300.

    it seems shift register that should shift for random number bits. How do you think synthesis tool could implent your code?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    It doesnt matter how enc_delay is calculated - quartus only supports slicing an array with a constant. And in your case your code implies slicing a variable number of bits out of an array, which is not possible with VHDL.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    You could rewrite your assignment with a for loop that goes through each bit of enc_delay and either shifts it or keeps it depending on the value of the index compared to cnt_clks.

    Do you really have a signal called "time" ? I'm surprised this doesn't conflict with the standard TIME type.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    Do you really have a signal called "time" ? I'm surprised this doesn't conflict with the standard TIME type.

    --- Quote End ---

    time is not a reserved keyword, nor are any type names. So you can use it to confuse yourself thoroughly (and it works because VHDL is all context driven)

    signal time : std_logic;

    signal std_logic : integer range 0 to 153;

    signal integer : real range -0.1 to 100.66;