error: expression is not constant

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Do you really have a signal called "time" ? I'm surprised this doesn't conflict with the standard TIME type.

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time is not a reserved keyword, nor are any type names. So you can use it to confuse yourself thoroughly (and it works because VHDL is all context driven)

signal time : std_logic;

signal std_logic : integer range 0 to 153;

signal integer : real range -0.1 to 100.66;