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Altera_Forum
Honored Contributor
Honored Contributorerror: expression is not constant
Hi, My code is as followed: signal cnt_clks : natural range 0 to 300;
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cnt_clks <= conv_integer(unsigned(time)) * 25;
process(clk_50,...
Altera_ForumHonored Contributor
Honored ContributorIt doesnt matter how enc_delay is calculated - quartus only supports slicing an array with a constant. And in your case your code implies slicing a variable number of bits out of an array, which is not possible with VHDL.
