Altera_Forum
Honored Contributor
10 years agoError 170084 ADC & PLL
Given:
Quartus 14.1.1 build190 BeMicro Max 10 10M08DAF484 System clock on N14 Error (170084): Can't route signal "ADC06:inst|ADC06_altpll_0:altpll_0|ADC06_altpll_0_altpll_5q22:sd1|wire_pll7_clk[0]" to atom "ADC06:inst|ADC06_ADC:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|primitive_instance" ADC.qip is the only file in the project and it consists of Qsys IP "Altera Modular ADC core, Avalon ALTPLL and JTAG to Avalon Master Bridge. I am having trouble compiling a the project using system clock on N14. If I compile the project on Clock pin N9 then compilation will complete without errors. What am I doing wrong? Thank you in advance. Mike