Forum Discussion
Honored Contributorerror -- Flash & NIOS2
Hello to all,
i built a stand alone electronics with an EP2C8 fpga and an 2MB flash-ram. I flashed my EPCS4 device with my current design. By the way, i purchased a license for MegaCore functions and i have installed the license. Now i want to flash the ram with the NIOS2 Flash Programmer, but it doesn't work. I got always the same error message.:( #!/bin/sh# # This file was automatically generated by the Nios II IDE Flash Programmer.# # It will be overwritten when the flash programmer options change.# cd C:/altera/FPGA_Projecte/Prj_ARCUS-ORBITER_FlashTest/software/hello_world_0/De bug # Creating .flash file for the project "$SOPC_KIT_NIOS2/bin/elf2flash" --base=0x00200000 --end=0x3fffff --reset=0x40200 0 --input="hello_world_0.elf" --output="cfi_flash.flash" --boot="C:/altera/81/ip /altera/nios2_ip/altera_nios2/boot_loader_cfi.srec" # Programming flash with the project "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00200000 --sidp=0x00405010 --id=1624484866 --timestamp=1246526067 "cfi_flash.flash" There are no Nios II processors available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary. Have you guys any suggestions to solve this problem??? Many thank's for your help... Manuel22 Replies
Altera_ForumNo problem... I let you know whitch mistake it was, and thank's for your help !!!!:)
- Altera_Forum
I'm afraid I'm out of ideas... The fact that you can read the CFI table in debug mode shows that the write signal is correctly connected to the flash, as you need it to go into CFI mode.
I don't think that it's necessary to create a pulse on the reset pin of the flash, but it certainly wouldn't hurt ;) - Altera_Forum
Could you take a look at the screen shot? On the right screen you will see
the read content of the flash-ram. I think the flash-ram works correctly. But on the left screen you see that the programming sequence failed. Could it be, the read sequence works and the write sequence doesn't??? - Altera_Forum
I'll try both. I have a 1MHz source on my board. I have also checked the hardware connection between the ram and the fpga. The reset pin has allways high signal, I hope that's okay. Could we find out more with the nios2 flash programmer command line mode ???
- Altera_Forum
You should have a special write (data 98h to address 55h) to enter CFI mode. It may come a lot later in your curve. Can you increase the buffer size and reduce the sampling clock frequency?
Or a better way could be to divide the buffer in several zones, each one of them triggered on an access. - Altera_Forum
Yes, I think so. I have a AT49BV163DT connected. The times for settling etc. in the sopc builder gui are set to 100 ns. I think a longer time than needed shouldn't be a problem. Suspicious is the one time write access to the flash ram. (PIC_Signal) There should be more than one write access, shouldn't it???
- Altera_Forum
The error message probably means that it's not able to communicate with the flash. Are you sure it is well connected?
You can also use a SignalTap II probe and see if the signals going to/from the flash are as expected. - Altera_Forum
No, I have done nothing after the generation. I think, I solved this problem...
At the first time I would flash the eeprom with the nios2 programm, but it doesn't work. ID error etc., because the jtag connection to my fpga had a fault. I realized it than I tried to flash the nios2 programm in the on_chip memory. I got the same ID and timestamp error as before. This morning I found the mistake and now it works. But could you tell me what a cfi table is ? #!/bin/sh# # This file was automatically generated by the Nios II IDE Flash Programmer.# # It will be overwritten when the flash programmer options change.# cd C:/Programm_ARCUS-OBITER_Handheld/software/hello_world_small_0/Release # Creating .flash file for the project "$SOPC_KIT_NIOS2/bin/elf2flash" --base=0x00200000 --end=0x3fffff --reset=0x40400 0 --input="hello_world_small_0.elf" --output="cfi_flash.flash" --boot="C:/altera /81/ip/altera/nios2_ip/altera_nios2/boot_loader_cfi.srec" # Programming flash with the project "$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00200000 --cable='USB-Blas ter [USB-0]' --device=1 --sidp=0x00409030 --id=1732617863 --timestamp=1246886060 "cfi_flash.flash" Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Resetting and pausing target processor: OK Reading System ID at address 0x00409030: verified <--- jipiiiie No CFI table found at address 0x00200000 Leaving target processor paused - Altera_Forum
That's really odd. I can't reproduce what you are describing... I have the same timestamp in the ptf and the sopc system.
Don't you do anything else after the generation? Something that would make SOPC builder think that you changed something in your system? - Altera_Forum
Yes, nobody is perfect, especially if it is the first design... and thank's daixiwen for your patience.
