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Altera_Forum's avatar
Altera_Forum
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15 years ago

Dual Port RAM Init

Hi,

I have generated a DPRAM with the Megawizard, and I have used it in my design.

When I have simulated it into Modelsim, all was ok. But when I have compiled my FPGA with my design, there was a problem. So I have used SignalTap to find the problem and I realized that my DPRAM wasn't initialized (with 0). So I have created a new ".hex" initialization memory file where I fixed all memory cases to '0'. And in the megawizard I have selected the ".hex" file link. But now when I compile my FPGA, that doesn't work, and I see that the DPRAM is not initialize into Signal Tap...

Someone already had this problem?

Thanks for your help =)

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    What are the memory related files that you use for synthesis? I had initialization problem in Qsys in simulation. I solved it by modifying the path of the `include in the <memory_name>.v file.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks for your answer Alteraaditya!

    For the synthesis I had added the ".vhd" file which has been created by Quartus, and the Megawizard had added the ".qip" file in my project.

    Do you think that my problem could come from here?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I am not sure, but if you are using Qsys a synthesis folder is created. In the same folder you have a .qip file. In the .qip file set the path of your memory file generated by Quartus [and make sure that your internalization file is included in your memory.vhd file]

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I don't use SOPC Builder. I just use Quartus for the compilation of my design. I have several VHDL files that I have created and I have used Altera IPs generated by MegaWizard.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    In the compilation report there is a section about RAM resources, that should give you a list of all the RAM blocs used by the design in the FPGA, their sizes and the file used for initialization. You should have a look there to check that your file was indeed used.

    Are you sure your hex file is the right size?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I downloaded spdif_intef pjt from open cores.i am trying to compile the code using questa sim.but it showing below error

    1.Library lpm not found.

    2. Unknown identifier "lpm".

    how to instansiate altera library .

    the error is showing ,when i compile a dpram_altera .

    i am waiting for ur replay
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    @ Nicoos

    Try to check your design in the ModelSim first, if the memory model is initialized by viewing the memory profile. Try to see if you are able to read the contents of the memory by initially setting the design in read mode.

    For example, in case while using single port ram megacore function, the altsyncram component should be synthesized and you will see the memory model.

    @ Kadiyam

    The error means that that you have not added the lpm library int o your work folder. You can get most of the components in the following folder (C:/altera/version/quartus/eda/sim_lib). Find the one which corresponds to your design.