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Altera_Forum's avatar
Altera_Forum
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15 years ago

Dual Port RAM Init

Hi, I have generated a DPRAM with the Megawizard, and I have used it in my design. When I have simulated it into Modelsim, all was ok. But when I have compiled my FPGA with my design, there w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for your answer Alteraaditya!

For the synthesis I had added the ".vhd" file which has been created by Quartus, and the Megawizard had added the ".qip" file in my project.

Do you think that my problem could come from here?