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Altera_Forum
Honored Contributor
15 years agoDual Port RAM Init
Hi, I have generated a DPRAM with the Megawizard, and I have used it in my design. When I have simulated it into Modelsim, all was ok. But when I have compiled my FPGA with my design, there w...
Altera_Forum
Honored Contributor
15 years agoI am not sure, but if you are using Qsys a synthesis folder is created. In the same folder you have a .qip file. In the .qip file set the path of your memory file generated by Quartus [and make sure that your internalization file is included in your memory.vhd file]